Radio communication apparatus and semiconductor device

Claim 2

A radio communication apparatus having a high-frequency power amplifier module at a transmitter-side output stage, and an antenna connected to said high-frequency power amplifier module, said high-frequency power amplifier module comprising: an input terminal; an output terminal; a control terminal; a first voltage terminal; a second voltage terminal; a power amplifier formed by connecting a plurality of transistors in parallel each of which has a first terminal, a second terminal and a control terminal for controlling a current flowing between said first and second terminals; first capacitors and first resistors connected in series between said input terminal and said control terminals of said transistors so that said capacitors are connected on said input terminal side while said resistors are connected on said control terminals side; and second resistors connected between said control terminal and the nodes of said first capacitors and said first resistors that are connected to said control terminals of said transistors, wherein said output terminal is connected to said first terminals of said transistors, said first voltage terminal to said first terminals of said transistors, and said second voltage terminal to said second terminals of said transistors.

Claim 3

A radio communication apparatus having a high-frequency power amplifier module at a transmitter-side output stage, and an antenna connected to said high-frequency power amplifier module, said high-frequency power amplifier module comprising: an input terminal; an output terminal; a control terminal; a first voltage terminal; a second voltage terminal; a power amplifier formed by connecting a plurality of transistors in parallel each of which has a first terminal, a second terminal and a control terminal for controlling a current flowing between said first and second terminals; first capacitors and first resistors connected in series between said input terminal and said control terminals of said transistors so that said capacitors are connected on said input terminal side while said resistors are connected on said control terminals side; second capacitors connected in parallel with said first resistors; and second resistors connected between said control terminal and the nodes of said first capacitors and said first resistors that are connected to said control terminals of said transistors, wherein said output terminal is connected to said first terminals of said transistors, said first voltage terminal to said first terminals of said transistors, and said second voltage terminal to said second terminals of said transistors.

Claim 4

A radio communication apparatus having a high-frequency power amplifier module at a transmitter-side output stage, and an antenna connected to said high-frequency power amplifier module, said high-frequency power amplifier module comprising: an input terminal; an output terminal; a control terminal; a first voltage terminal; a second voltage terminal; a power amplifier formed by connecting a plurality of transistors in parallel each of which has a first terminal, a second terminal and a control terminal for controlling a current flowing between said first and second terminals; first capacitors and first resistors connected in series between said input terminal and said control terminals of said transistors so that said capacitors are connected on said input terminal side while said resistors are connected on said control terminals side; second capacitors connected in parallel with said first resistors; and second resistors connected between said control terminal and the nodes of said first capacitors and said first resistors that are connected to said control terminals of said transistors, wherein said output terminal is connected to said first terminals of said transistors, said first voltage terminal to said first terminals of said transistors, and said second voltage terminal to said second terminals of said transistors.

Claim 5

A radio communication apparatus according to claim 2 , wherein the DC voltage drop across each of said transistors in operation is about 0.15 V or below, the resistance value of each of said first resistors is about 1 Ω or below and the capacitance value of each of said second capacitors is about 5 pF or below.

Claim 6

A radio communication apparatus according to claim 1 , wherein said high-frequency power amplifier module is of a multi-stage arrangement in which a plurality of said power amplifiers are sequentially connected in cascade, so that said control terminals of said transistors of a first-stage one of said power amplifiers are connected to said input terminal, said first terminals of said transistors of a last-stage one of said power amplifiers are connected to said output terminal, said control terminals of said transistors of an intermediate-stage one of said power amplifiers are connected to said first terminals of said transistors of the previous-stage one of said power amplifiers, said first terminals being connected to said control terminals of said transistors of the following-stage one of said power amplifiers, at least one of said first-stage, intermediate-stage and last-stage power amplifiers has said first capacitors, said first resistors and said second resistors incorporated therein, and a predetermined control voltage is supplied to said control terminals of said power amplifiers.

Claim 7

A radio communication apparatus according to claim 2 , wherein said high-frequency power amplifier module is of a multi-stage arrangement in which a plurality of said power amplifiers are sequentially connected in cascade, so that said control terminals of said transistors of a first-stage one of said power amplifiers are connected to said input terminal, said first terminals of said transistors of a last-stage one of said power amplifiers are connected to said output terminal, said control terminals of said transistors of an intermediate-stage one of said power amplifiers are connected to said first terminals of said transistors of the previous-stage one of said power amplifiers, said first terminals being connected to said control terminals of said transistors of the following-stage one of said power amplifiers, at least one of said first-stage, intermediate-stage and last-stage power amplifiers has said first capacitors, said first resistors and said second resistors and said second capacitors incorporated therein, and a predetermined control voltage is supplied to said control terminals of said power amplifiers.

Claim 8

A radio communication apparatus according to claim 1 , wherein inductors are respectively connected between said control terminal and said second resistors.

Claim 9

A radio communication apparatus according to claim 1 , wherein inductors are respectively connected between said second voltage terminal and said second terminals.

Claim 10

A radio communication apparatus according to claim 1 , wherein said transistors constituting said power amplifier are monolithically formed on a single semiconductor substrate.

Claim 11

A radio communication apparatus according to claim 8 , wherein a sensor transistor constituting a current-mirror circuit is monolithically formed on said semiconductor substrate.

Claim 12

A radio communication apparatus according to claim 8 , wherein a sensor diode constituting a current-mirror circuit is monolithically formed on said semiconductor substrate.

Claim 13

A radio communication apparatus having a high-frequency power amplifier module at a transmitter-side output stage, and an antenna connected to said high-frequency power amplifier module, said high-frequency power amplifier module comprising: an input terminal; an output terminal; a control terminal; a first voltage terminal; a second voltage terminal; a power amplifier formed by connecting a plurality of transistors in parallel each of which has a first terminal, a second terminal and a control terminal for controlling a current flowing between said first and second terminals; a single second capacitor and first resistors connected in series between said input terminal and said control terminals of said transistors so that said capacitor is connected on said input terminal side while said resistors are connected on said control terminals side; and a single second resistor having one end connected in series with each of said first resistors and the other end connected to said control terminal, wherein said output terminal is connected to said first terminals of said transistors, said first voltage terminal to said first terminals of said transistors, and said second voltage terminal to said second terminals of said transistors.

Claim 14

A radio communication apparatus having a high-frequency power amplifier module at a transmitter-side output stage, and an antenna connected to said high-frequency power amplifier module, said high-frequency power amplifier module comprising: an input terminal; an output terminal; a control terminal; a first voltage terminal; a second voltage terminal; a power amplifier formed by connecting a plurality of transistors in parallel each of which has a first terminal, a second terminal and a control terminal for controlling a current flowing between said first and second terminals; a single second capacitor and first resistors connected in series between said input terminal and said control terminals of said transistors so that said capacitor is connected on said input terminal side while said resistors are connected on said control terminals side; and a single second resistor having one end connected in series with each of said first resistors and the other end connected to said control terminal, wherein said output terminal is connected to said first terminals of said transistors, said first voltage terminal to said first terminals of said transistors, and said second voltage terminal to said second terminals of said transistors.

Claim 15

A radio communication apparatus according to claim 11 , wherein one block or a plurality of blocks each of which is formed of a plurality of transistors that constitute said power amplifier are arranged, and said first capacitor and said second resistor are provided for each block.

Claim 16

A radio communication apparatus according to claim 12 , wherein the thermal resistance difference between the transistors within each block is smaller than the thermal resistance of said power amplifier.

Claim 17

A radio communication apparatus according to claim 13 , wherein the ratio of the thermal resistance of said power amplifier to the thermal resistance difference between the transistors within each block is equal to or less than about ½ the ratio of the sum of said second resistance and the parallel resistance of said first resistors to the parallel resistance of said first resistors connected in parallel within each block.

Claim 18

A semiconductor device comprising: an input terminal; an output terminal; a bias terminal; a power amplifier formed by connecting a plurality of transistors each having a first terminal, a second terminal and a control terminal for controlling the current flowing between said first terminal and said second terminal; first capacitors C 2A ˜C 2N connected between said input terminal and said control terminals of said transistors and connected to said input terminal, and first resistors R 1A ˜R 1N connected in series with said first capacitors C 2A ˜C 2N , and connected to said control terminals of said transistors; and second resistors R 2A ˜R 2N connected between said bias terminal and said control terminals of said transistors, and connected to the nodes of said first resistors R 1A ˜R 1N and said first capacitors C 2A ˜C 2N , said output terminal being connected to said first terminals of said transistors.

Claim 19

A semiconductor device comprising: an input terminal; an output terminal; a bias terminal; a power amplifier formed by connecting a plurality of transistors each having a first terminal, a second terminal and a control terminal for controlling the current flowing between said first terminal and said second terminal; first capacitors C 2A ˜C 2N connected between said input terminal and said control terminals of said transistors and connected to said input terminal, and first resistors R 1A ˜R 1N connected in series with said first capacitors C 2A ˜C 2N , and connected to said control terminals of said transistors; and second resistors R 2A ˜R 2N connected between said bias terminal and said control terminals of said transistors, and connected to the nodes of said first resistors R 1A ˜R 1N and said first capacitors C 2A ˜C 2N , said output terminal being connected to said first terminals of said transistors.

Claim 20

A semiconductor device according to claim 15 , wherein second capacitors C 1A ˜C 1N are provided to be connected in parallel with said first resistors R 1A ˜R 1N .

Claim 21

A semiconductor device comprising: the terminal; an output terminal; a bias terminal; a power amplifier formed by connecting a plurality of transistors each having a first terminal, a second terminal and a control terminal for controlling the current flowing between said first terminal and said second terminal; a single first capacitor C 2 connected between said input terminal and said control terminals of said transistors and connected to said input terminal, and first resistors R 1A ˜R 1N connected in series with said first capacitor C 2 , and connected to said control terminals of said transistors; and a single second resistor R 2 connected between said bias terminal and said control terminals of said transistors, and connected to the nodes of said first resistors R 1A ˜R 1N and said first capacitor C 2 , said output terminal being connected to said first terminals of said transistors.

Claim 22

A semiconductor device comprising: the terminal; an output terminal; a bias terminal; a power amplifier formed by connecting a plurality of transistors each having a first terminal, a second terminal and a control terminal for controlling the current flowing between said first terminal and said second terminal; a single first capacitor C 2 connected between said input terminal and said control terminals of said transistors and connected to said input terminal, and first resistors R 1A ˜R 1N connected in series with said first capacitor C 2 , and connected to said control terminals of said transistors; and a single second resistor R 2 connected between said bias terminal and said control terminals of said transistors, and connected to the nodes of said first resistors R 1A ˜R 1N and said first capacitor C 2 , said output terminal being connected to said first terminals of said transistors.

Claim 23

A semiconductor device according to claim 17 , wherein second capacitors C 1A ˜C 1N are provided to be connected in parallel with said first resistors R 1A ˜R 1N .

Claim 24

A semiconductor device according to claim 15 , wherein the DC voltage drop across each of said transistors in operation is about 0.15 V or below, the resistance value of each of said first resistors is about 1 Ω or below and the capacitance value of each of said second capacitors is about 5 pF or below.

Claim 25

A semiconductor device according to claim 15 , wherein a sensor transistor constituting a current-mirror circuit is monolithically formed on said semiconductor substrate in which said semiconductor device is formed.

Claim 26

A semiconductor device according to claim 15 , wherein one block or a plurality of blocks each of which is formed of a plurality of transistors that constitute said power amplifier are arranged, and said first capacitor and said second resistor are provided for each block.

Claim 27

A semiconductor device according to claim 21 , wherein the thermal resistance difference between the transistors within each block is smaller than the thermal resistance of said power amplifier.

Claim 28

A semiconductor device according to claim 21 , wherein the ratio of the thermal resistance of said power amplifier to the thermal resistance difference between the transistors within each block is equal to or less than about ½ the ratio of the sum of said second resistance and the parallel resistance of said first resistors to the parallel resistance of said first resistors connected in parallel within each block.