Abstract A digital delay line, which includes a plurality of multiplexer delay elements, arranged in sequence with each of the plurality of multiplexer delay elements having an associated control input. A clock signal line is coupled to a clock input of each of the plurality of multiplexers and is operative to provide synchronous, phase aligned clock signals from a clock signal source to each of said clock inputs. A control input is coupled to each of the plurality of multiplexer delay elements and is operative to transmit to each of the plurality of multiplexer delay elements an associated control signal. In response to a first change in the control signal an associated delay element is added to the delay line and in response to a second change the delay element is removed from the delay line.
A method of establishing a digital delay line, comprising: (a) forming a sequence of digital delay elements; (b) coupling a control bus to each of said delay elements, control signals on said control bus being operative to control the selection or deselection of associated delay elements from proximate a start of said delay line; (c) coupling an input clock to each of said digital delay elements by using an input clock bus; wherein two or more delay elements are selected or deselected in a single step, proximate an input side of said sequence of delay elements.
Claim 2
Independent Claim
96 words
A method of establishing a digital delay line, comprising: (a) forming a sequence of digital delay elements; (b) coupling a control bus to each of said delay elements, control signals on said control bus being operative to control the selection or deselection of associated delay elements from proximate a start of said delay line; (c) coupling an input clock to each of said digital delay elements by using an input clock bus; wherein two or more delay elements are selected or deselected in a single step, proximate an input side of said sequence of delay elements.
Claim 3
Dependent Claim
22 words
The method according to claim 1 , wherein said digital delay elements is a multiplexer formed from a combination of logic gates.
Claim 4
Dependent Claim
27 words
The method according to claim 1 , wherein each of said logic gates is selected from the group consisting of a NAND gate and a NOR gate.
Claim 5
Dependent Claim
20 words
The method according to claim 2 , including interfacing a flip-flop between said control bus and each of said multiplexers.