Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit, comprising: a first circuit for receiving a first clock signal and a second clock signal and for activating a first phase difference signal corresponding to a phase difference between the first clock signal and the second clock signal when a phase of the first clock signal is delayed by more than a predetermined value in comparison with a phase of the second clock signal and activating a second phase difference signal corresponding to the phase difference when the phase of the first clock signal is advanced by more than a predetermined value in comparison with the phase of the second clock signal; a second circuit for receiving the first clock signal and the second clock signal and for activating a first pulse signal when an edge of the first clock signal is delayed in comparison with an edge of the second clock signal and activating a second pulse signal when the edge of the first clock signal is advanced in comparison with the edge of the second clock signal; a third circuit for combining the first phase difference signal output from said first circuit and the first pulse signal output from said second circuit; and a fourth circuit for combining the second phase difference signal output from said first circuit and the second pulse signal output from said second circuit.

Claim 3

A semiconductor integrated circuit according to claim 1 , wherein said second circuit activates the first pulse signal for a fixed period regardless of the phase difference between the first clock signal and the second clock signal in the case where the edge of the first clock signal is delayed in comparison with the edge of the second clock signal and activates the second pulse signal for a fixed period regardless of the phase difference in the case where the edge of the first clock signal is advanced in comparison with the edge of the second clock signal.

Claim 4

A semiconductor integrated circuit according to claim 1 , wherein said third circuit includes an OR circuit for subjecting the first phase difference signal output from said first circuit and the first pulse signal output from said second circuit to a logical OR operation, and said fourth circuit includes an OR circuit for subjecting the second phase difference signal output from said first circuit and the second pulse signal output from said second circuit to a logical OR operation.

Claim 5

A PLL (phase locked loop) circuit comprising a phase comparator means, said phase comparator means comprising: a phase comparator circuit for receiving a first clock signal and a second clock signal and for activating a first phase difference signal corresponding to a phase difference between the first clock signal and the second clock signal when a phase of the first clock signal is delayed by more than a predetermined value in comparison with a phase of the second clock signal and activating a second phase difference signal corresponding to the phase difference when the phase of the first clock signal is advanced by more than a predetermined value in comparison with the phase of the second clock signal; an arbitration circuit for receiving the first clock signal and the second clock signal and for activating a first pulse signal whdn an edge of the first clock signal is delayed in comparison with an edge of the second clock signal and activating a second pulse signal when the edge of the first clock signal is advanced in comparison with the edge of the second clock signal, said arbitration circuit comprising an edge detection circuit for detecting a rising edge of one of the first and second clock signals being advanced and a pulse generating circuit for generating one of the first and second pulse signals; a first combining circuit for combining the first phase difference signal output from said phase comparator circuit and the first pulse signal output from said arbitration circuit; and a second combining circuit for combining the second phase difference signal output from said phase comparator circuit and the second pulse signal output from said arbitration circuit.

Claim 6

A PLL (phase locked loop) circuit comprising a phase comparator means, said phase comparator means comprising: a phase comparator circuit for receiving a first clock signal and a second clock signal and for activating a first phase difference signal corresponding to a phase difference between the first clock signal and the second clock signal when a phase of the first clock signal is delayed by more than a predetermined value in comparison with a phase of the second clock signal and activating a second phase difference signal corresponding to the phase difference when the phase of the first clock signal is advanced by more than a predetermined value in comparison with the phase of the second clock signal; an arbitration circuit for receiving the first clock signal and the second clock signal and for activating a first pulse signal whdn an edge of the first clock signal is delayed in comparison with an edge of the second clock signal and activating a second pulse signal when the edge of the first clock signal is advanced in comparison with the edge of the second clock signal, said arbitration circuit comprising an edge detection circuit for detecting a rising edge of one of the first and second clock signals being advanced and a pulse generating circuit for generating one of the first and second pulse signals; a first combining circuit for combining the first phase difference signal output from said phase comparator circuit and the first pulse signal output from said arbitration circuit; and a second combining circuit for combining the second phase difference signal output from said phase comparator circuit and the second pulse signal output from said arbitration circuit.

Claim 7

A PLL circuit according to claim 4 , wherein: said edge detection circuit comprises NAND circuits, a first inverter including a P-channel transistor and an N-channel transistor, and a second inverter including a P-channel transistor and an N-channel transistor; and said pulse generating circuit comprises inverters and AND circuits.

Claim 8

A DLL (delay locked loop) circuit comprising a phase comparator means, said phase comparator means comprising: a phase comparator circuit for receiving a first clock signal and a second clock signal and for activating a first phase difference signal corresponding to a phase difference between the first clock signal and the second clock signal when a phase of the first clock signal is delayed by more than a predetermined value in comparison with a phase of the second clock signal and activating a second phase difference signal corresponding to the phase difference when the phase of the first CLOCK signal is advanced by more than a predetermined value in comparison with the phase of the second clock signal; an arbitration circuit for receiving the first clock signal and the second clock signal and for activating a first pulse signal when an edge of the first clock signal is delayed in comparison with an edge of the second clock signal and activating a second pulse signal when the edge of the first clock signal is advanced in comparison with the edge of the second clock signal, said arbitration circuit comprising an edge detection circuit for detecting a rising edge of one of the first and second clock signals being advanced and a pulse generating circuit for generating one of the first and second pulse signals; a first combining circuit for combining the first phase difference signal output from said phase comparator circuit and the first pulse signal output from said arbitration circuit; and a second combining circuit for combining the second phase difference signal output from said phase comparator circuit and the second pulse signal output from said arbitration circuit.

Claim 9

A DLL (delay locked loop) circuit comprising a phase comparator means, said phase comparator means comprising: a phase comparator circuit for receiving a first clock signal and a second clock signal and for activating a first phase difference signal corresponding to a phase difference between the first clock signal and the second clock signal when a phase of the first clock signal is delayed by more than a predetermined value in comparison with a phase of the second clock signal and activating a second phase difference signal corresponding to the phase difference when the phase of the first CLOCK signal is advanced by more than a predetermined value in comparison with the phase of the second clock signal; an arbitration circuit for receiving the first clock signal and the second clock signal and for activating a first pulse signal when an edge of the first clock signal is delayed in comparison with an edge of the second clock signal and activating a second pulse signal when the edge of the first clock signal is advanced in comparison with the edge of the second clock signal, said arbitration circuit comprising an edge detection circuit for detecting a rising edge of one of the first and second clock signals being advanced and a pulse generating circuit for generating one of the first and second pulse signals; a first combining circuit for combining the first phase difference signal output from said phase comparator circuit and the first pulse signal output from said arbitration circuit; and a second combining circuit for combining the second phase difference signal output from said phase comparator circuit and the second pulse signal output from said arbitration circuit.

Claim 10

A DLL circuit according to claim 6 , wherein: said edge detection circuit comprises NAND circuits, a first inverter including a P-channel transistor and an N-channel transistor, and a second inverter including a P-channel transistor and an N-channel transistor; and said pulse generating circuit comprises inverters and AND circuits.