Patent US6762615B2 successfully refreshed from Google Patents.
US6762615B2
Expired / Lapsed
US
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Parallel test board used in testing semiconductor memory devices
Assignee: Samsung Electronics Co Ltd
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Filing: 2002-03-08
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Granted: 2004-07-13
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Expires: 2022-03-08
Abstract
Abstract A parallel test board preferably includes a plurality of serial slots connected to a motherboard and a number of parallel slots connected to the motherboard in parallel with each other. The motherboard provides an actual operational environment for devices under test (DUTs). DUTs are mounted in the slots. Using a plurality of serial slots, distorted timings due to one serial slot (e.g., an extension slot) have an influence on the other serial slot (e.g., a reference slot), as well as on the parallel slots. In this manner, a timing margin failure occurring during a multi-bank operation can be effectively detected. The slots to which the DUTs are mounted preferably have a socket structure with a support block having contact pins arranged thereon. Each of the contact pins preferably has a module contact part configured to contact a tab of the DUT and a board contact part configured to contact conductive wiring patterns of an intermediation board. An elastic member is also preferably interposed between the support block and each of the module and the board contact parts. According to various aspects and embodiments of this invention, testing reliability is improved and the durability of the test board is significantly increased.
Inventors
- 👤 Man-Heung Lee
- 👤 Chang-Ho Lee
- 👤 Sang-Chul Yun
- 👤 Si-Don Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:39
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56; G01; G01R; G01R1/00; G01R1/02; G01R1/04; G01R1/0408; G01R1/0433; G01R1/0441; G01R1/045; G11C29/04; G11C29/08; G11C29/48
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
158 words
A parallel test board configured to perform test sequences by connecting a plurality of semiconductor devices under test (DUTs) to a motherboard, said motherboard configured to provide an actual operational environment for the DUTs, said parallel test board comprising: an intermediation board having conductive wiring patterns and configured to electrically interconnect the DUTs to the motherboard; a reference slot mounted to the intermediation board and configured to receive one or more of the DUTs, wherein said reference slot is electrically connected to the motherboard; an extension slot mounted to the intermediation board and configured to receive one or more of the DUTs, wherein said extension slot is electrically connected to the motherboard and wherein the extension slot has the same configuration as the reference slot; and a plurality of parallel slots connected in parallel to the reference slot, wherein said parallel slots are mounted to the intermediation board and configured to receive one or more of the DUTs.
Claim 2
Dependent Claim
158 words
A parallel test board configured to perform test sequences by connecting a plurality of semiconductor devices under test (DUTs) to a motherboard, said motherboard configured to provide an actual operational environment for the DUTs, said parallel test board comprising: an intermediation board having conductive wiring patterns and configured to electrically interconnect the DUTs to the motherboard; a reference slot mounted to the intermediation board and configured to receive one or more of the DUTs, wherein said reference slot is electrically connected to the motherboard; an extension slot mounted to the intermediation board and configured to receive one or more of the DUTs, wherein said extension slot is electrically connected to the motherboard and wherein the extension slot has the same configuration as the reference slot; and a plurality of parallel slots connected in parallel to the reference slot, wherein said parallel slots are mounted to the intermediation board and configured to receive one or more of the DUTs.
Claim 3
Dependent Claim
29 words
The parallel test board of claim 1 , wherein the motherboard is configured to control the DUTs mounted in the reference and extension slots through an external bank operation.
Claim 4
Dependent Claim
36 words
The parallel test board of claim 1 , wherein the motherboard includes a CPU that is configured to provide address signals, control signals, and data input signals to DUTs mounted in the reference and extension slots.
Claim 5
Dependent Claim
47 words
The parallel test board of claim 1 , wherein the motherboard is configured to control read and write operations performed to DUTs mounted in the plurality of parallel slots at the same time read and write operations are performed to the DUTs mounted in the reference slot.
Claim 6
Dependent Claim
76 words
The parallel test board of claim 4 , wherein the DUTs are memory modules and wherein the motherboard comprises: a first PLL clock driver configured to provide a clock signal to the memory modules mounted in the reference and extension slots; and a second PLL clock driver configured to receive an output signal from the first PLL clock driver and to provide a clock signal to the memory modules mounted in the plurality of parallel slots.
Claim 7
Dependent Claim
40 words
The parallel test board of claim 4 , wherein the DUTs are memory modules and wherein the motherboard comprises a buffer configured to provide address signals and control signals to the memory modules mounted in the plurality of parallel slots.
Claim 8
Dependent Claim
66 words
The parallel test board of claim 4 , wherein the DUTs are memory modules and wherein the motherboard comprises: a second buffer configured to provide data to the memory modules mounted in the plurality of parallel slots; and a comparator configured to compare output data from the memory module devices with reference data and to determine if the output data is identical to the reference data.
Claim 9
Dependent Claim
55 words
The parallel test board of claim 1 , wherein the motherboard comprises a front side and a backside, said backside arranged opposite the front side, wherein the front side has electronic components mounted thereon, wherein said electronic components comprise a CPU, and wherein the parallel test board is mounted to the backside of the motherboard.
Claim 10
Dependent Claim
176 words
A parallel test board configured to perform test sequences by connecting a plurality of semiconductor devices under test (DUTs) to a motherboard, said motherboard configured to provide an actual operational environment for the DUTs, said parallel test board comprising: an intermediation board having conductive wiring patterns and configured to electrically interconnect the DUTs to the motherboard; a reference slot mounted to the intermediation board and configured to receive one or more of the DUTs, wherein said reference slot is electrically connected to the motherboard; an extension slot mounted to the intermediation board and configured to receive one or more of the DUTs, wherein said extension slot is electrically connected to the motherboard; a plurality of parallel slots connected in parallel to the reference slot, wherein said parallel slots are mounted to the intermediation board and configured to receive one or more of the DUTs, wherein the reference slot, the extension slot, and the parallel slots each comprise a socket structure, said socket structure comprising a support block having contact pins arranged in the same configuration thereon.
Claim 11
Dependent Claim
176 words
A parallel test board configured to perform test sequences by connecting a plurality of semiconductor devices under test (DUTs) to a motherboard, said motherboard configured to provide an actual operational environment for the DUTs, said parallel test board comprising: an intermediation board having conductive wiring patterns and configured to electrically interconnect the DUTs to the motherboard; a reference slot mounted to the intermediation board and configured to receive one or more of the DUTs, wherein said reference slot is electrically connected to the motherboard; an extension slot mounted to the intermediation board and configured to receive one or more of the DUTs, wherein said extension slot is electrically connected to the motherboard; a plurality of parallel slots connected in parallel to the reference slot, wherein said parallel slots are mounted to the intermediation board and configured to receive one or more of the DUTs, wherein the reference slot, the extension slot, and the parallel slots each comprise a socket structure, said socket structure comprising a support block having contact pins arranged in the same configuration thereon.
Claim 12
Dependent Claim
43 words
The parallel test board of claim 9 , wherein each of the contact pins includes a module contact part configured to contact to a tab of the DUTs and a board contact part configured to contact a conductive pattern of the intermediation board.
Claim 13
Dependent Claim
41 words
The parallel test board of claim 10 , wherein a first elastic member is interposed between the module contact part and the support block, and wherein a second elastic member is interposed between the board contact part and the support block.
Claim 14
Dependent Claim
24 words
The parallel test board of claim 11 , wherein the board contact part of the contact pin substantially wraps around the second elastic member.
Claim 15
Dependent Claim
17 words
The parallel test board of claim 9 , wherein the slots are bolt-coupled to the intermediation board.
Claim 16
Dependent Claim
23 words
The parallel test board of claim 9 , wherein the intermediation board comprises connectors configured to pin-connect the intermediation board to the motherboard.
Claim 17
Dependent Claim
48 words
The parallel test board of claim 9 , wherein the socket structure further comprises a housing configured to receive the contact pins and the support block, wherein said housing is configured to receive one of the DUTs, and wherein the housing comprises separation handles protruding from ends thereof.
Claim 18
Dependent Claim
16 words
The parallel test board of claim 9 , wherein the intermediation board comprises a multi-layered structure.
Claim 19
Dependent Claim
41 words
The parallel test board of claim 9 , wherein the reference slot, the extension slot, and the parallel slots are arranged in parallel to each other on the intermediation board, and wherein the slots are arranged having an irregular spacing therebetween.
Claim 20
Dependent Claim
65 words
The parallel test board of claim 9 , wherein the socket structure comprises a housing configured to receive the contact pins and the support block, wherein said housing comprises two vertical members and a horizontal member arranged in approximately an “H” shape, wherein said horizontal member comprises an opening, and wherein said opening is configured to receive one of the DUTs inserted into the slot.
Claim 21
Dependent Claim
65 words
The parallel test board of claim 9 , wherein the socket structure comprises a housing configured to receive the contact pins and the support block, wherein said housing comprises two vertical members and a horizontal member arranged in approximately an ‘H’ shape, and wherein a supplemental block is interposed between the support block and the vertical member to enlarge the width of the socket structure.
Claim 22
Dependent Claim
73 words
The parallel test board of claim 9 , wherein the socket structure comprises a housing configured to receive the contact pins and the support block, said housing comprising two vertical members and a horizontal member arranged in approximately an ‘H’ shape, and wherein the vertical members comprise lower sections arranged below the horizontal member that are thicker than upper sections located above the horizontal member to enlarge the width of the socket structure.
Claim 23
Independent Claim
61 words
A method of testing a plurality of memory modules in parallel under actual operating conditions, said method comprising: arranging a plurality of test slots on a test board; arranging at least two test slots in electrical communication with a motherboard; arranging at least one test slot in parallel with the at least two test slots in electrical communication with the motherboard.
Claim 24
Independent Claim
61 words
A method of testing a plurality of memory modules in parallel under actual operating conditions, said method comprising: arranging a plurality of test slots on a test board; arranging at least two test slots in electrical communication with a motherboard; arranging at least one test slot in parallel with the at least two test slots in electrical communication with the motherboard.
Claim 25
Dependent Claim
30 words
The method of claim 21 , wherein arranging at least two test slots in electrical communication with a motherboard comprises arranging a reference slot in electrical communication with the motherboard.
Claim 26
Dependent Claim
30 words
The method of claim 21 , wherein arranging at least two test slots in electrical communication with a motherboard comprises arranging an extension slot in electrical communication with the motherboard.
Claim 27
Dependent Claim
41 words
The method of claim 21 , wherein arranging at least one test slot in parallel with the at least two test slots in electrical communication with the motherboard comprises arranging a plurality of parallel test slots to communicate with the motherboard.
Claim 28
Dependent Claim
23 words
The method of claim 21 , further comprising arranging the test slots on the test board such that they have an irregular spacing.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-07-13 | 2008-01-12 | 2008-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-07-13 | 2012-01-12 | 2012-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-07-13 | 2016-01-12 | 2016-07-13 | $7700.00 | Window Closed / Lapsed |