MOSFET with SiGe source/drain regions and epitaxial gate dielectric

Claim 2

A semiconductor device formed on a substrate and comprising: a well, said well comprising two silicon germanium filled spaces and a remaining portion, said remaining portion of said well not comprising silicon germanium; a channel region of first conductivity type and being in the well; a dielectric layer overlying the channel region; and a gate electrode overlying the dielectric layer; wherein said two silicon germanium filled spaces comprise respective source/drain regions of second conductivity type, said respective source/drain regions being situated on opposite sides of the channel region.

Claim 3

The device of claim 1 wherein the gate electrode comprises a metal.

Claim 4

The device of claim 1 wherein each of the source/drain regions has a depth of about 100 to about 1000 Angstroms.

Claim 5

The device of claim 1 wherein the source/drain regions comprise amorphous material.

Claim 6

A semiconductor device formed on a substrate and comprising: a well; a channel region of first conductivity type and being in said well; a dielectric layer overlying said channel region; a diffusion barrier layer overlying said dielectric layer; a gate electrode overlying said diffusion barrier layer; a blocking layer overlying said gate electrode; and two source/drain regions of second conductivity type formed on opposite sides of said channel region; wherein each of said dielectric layer, said diffusion barrier layer, and said blocking layer comprise epitaxial layers.

Claim 7

A semiconductor device formed on a substrate and comprising: a well; a channel region of first conductivity type and being in said well; a dielectric layer overlying said channel region; a diffusion barrier layer overlying said dielectric layer; a gate electrode overlying said diffusion barrier layer; a blocking layer overlying said gate electrode; and two source/drain regions of second conductivity type formed on opposite sides of said channel region; wherein each of said dielectric layer, said diffusion barrier layer, and said blocking layer comprise epitaxial layers.

Claim 8

The device of claim 5 wherein said gate electrode comprises silicon germanium.

Claim 9

The device of claim 5 wherein each of said source/drain regions comprises silicon germanium.

Claim 10

The device of claim 5 wherein each of said source/drain regions comprises amorphous silicon germanium.

Claim 11

The device of claim 5 wherein said dielectric layer is selected from the group consisting of oxides of zircon, oxides of titanium, oxides of tantalum, and oxides of hafnium.

Claim 12

The device of claim 5 wherein said blocking layer comprises less than or equal to ten atomic monolayers.

Claim 13

The device of claim 5 wherein said diffusion barrier layer comprises less than or equal to ten atomic monolayers.

Claim 14

A semiconductor device formed on a substrate and comprising: a well; a channel region of first conductivity type and being in the well; a dielectric layer overlying the channel region; a diffusion barrier layer directly overlying and in contact with the dielectric layer, said diffusion barrier layer being a single layer; a gate electrode directly overlying and in contact with the diffusion barrier layer, said gate electrode layer comprising a semiconductor material; a blocking layer overlying the gate electrode; two source/drain regions of second conductivity type formed on opposite sides of the channel region; wherein each of the dielectric layer, the diffusion barrier layer, and the blocking layer comprise epitaxial layers.

Claim 15

A semiconductor device formed on a substrate and comprising: a well; a channel region of first conductivity type and being in the well; a dielectric layer overlying the channel region; a diffusion barrier layer directly overlying and in contact with the dielectric layer, said diffusion barrier layer being a single layer; a gate electrode directly overlying and in contact with the diffusion barrier layer, said gate electrode layer comprising a semiconductor material; a blocking layer overlying the gate electrode; two source/drain regions of second conductivity type formed on opposite sides of the channel region; wherein each of the dielectric layer, the diffusion barrier layer, and the blocking layer comprise epitaxial layers.

Claim 16

A semiconductor device formed on a substrate and comprising: a well; a channel region of first conductivity type and being in the well; a dielectric layer overlying the channel region; a diffusion barrier layer directly overlying and in contact with the dielectric layer, said diffusion barrier layer being a single layer; a gate electrode directly overlying and in contact with the diffusion barrier layer, said gate electrode layer comprising a semiconductor material; a blocking layer overlying the gate electrode; two source/drain regions of second conductivity type formed on opposite sides of the channel region; wherein the gate electrode comprises silicon germanium.

Claim 17

A semiconductor device formed on a substrate and comprising: a well; a channel region of first conductivity type and being in the well; a dielectric layer overlying the channel region; a diffusion barrier layer directly overlying and in contact with the dielectric layer, said diffusion barrier layer being a single layer; a gate electrode directly overlying and in contact with the diffusion barrier layer, said gate electrode layer comprising a semiconductor material; a blocking layer overlying the gate electrode; two source/drain regions of second conductivity type formed on opposite sides of the channel region; wherein the gate electrode comprises silicon germanium.

Claim 18

A semiconductor device formed on a substrate and comprising: a well; a channel region of first conductivity type and being in the well; a dielectric layer overlying the channel region; a diffusion barrier layer directly overlying and in contact with the dielectric layer, said diffusion barrier layer being a single layer; a gate electrode directly overlying and in contact with the diffusion barrier layer, said gate electrode layer comprising a semiconductor material; a blocking layer overlying the gate electrode; two source/drain regions of second conductivity type formed on opposite sides of the channel region; wherein each of the source/drain regions comprises silicon germanium.

Claim 19

A semiconductor device formed on a substrate and comprising: a well; a channel region of first conductivity type and being in the well; a dielectric layer overlying the channel region; a diffusion barrier layer directly overlying and in contact with the dielectric layer, said diffusion barrier layer being a single layer; a gate electrode directly overlying and in contact with the diffusion barrier layer, said gate electrode layer comprising a semiconductor material; a blocking layer overlying the gate electrode; two source/drain regions of second conductivity type formed on opposite sides of the channel region; wherein each of the source/drain regions comprises silicon germanium.

Claim 20

The device of claim 14 wherein each of the source/drain regions comprises amorphous silicon germanium.