US6255698B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit
Assignee: GlobalFoundries Inc
•
Filing: 1999-04-28
•
Granted: 2001-07-03
•
Expires: 2019-04-28
Abstract
Abstract An integrated circuit containing separately optimized gate structures for n-channel and p-channel transistors is provided and formed. Original gate structures for both n-channel and p-channel transistors are patterned over appropriately-doped active regions of a semiconductor substrate. Protective dielectrics are formed over the semiconductor substrate to the same elevation level as the upper surfaces of the original gate structures, so that only the upper surfaces of the gate structures are exposed. A masking layer is used to cover the gate structures of either the p-channel or the n-channel transistors. The uncovered gate structures are removed, forming a trench within the protective dielectric in place of each removed gate structure. The trenches are refilled with a new gate structure which is preferably optimized for operation of the appropriate transistor type (n-channel or p-channel).
Inventors
- 👤 Mark I. Gardner
- 👤 H. Jim Fulford, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:29
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0177; H10D84/02; H10D84/03; H10D84/038; H10D64/00; H10D64/01; H10D64/017
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
126 words
An integrated circuit, comprising: an n-type active region of a semiconductor substrate separated from a p-type active region of said substrate by an isolation region; an n-channel transistor comprising a first gate structure arranged above said p-type active region, wherein said first gate structure comprises a first gate conductor in direct contact with a first gate dielectric, and wherein said first rate conductor comprises a low-temperature metal; and a p-channel transistor comprising a second gate structure arranged above said n-type active region, wherein said second gate structure comprises a second gate conductor over a second gate dielectric, and wherein said second gate conductor comprises a low-temperature metal, and wherein a composition of said second gate structure is different than a composition of said first gate structure.
Claim 2
Dependent Claim
126 words
An integrated circuit, comprising: an n-type active region of a semiconductor substrate separated from a p-type active region of said substrate by an isolation region; an n-channel transistor comprising a first gate structure arranged above said p-type active region, wherein said first gate structure comprises a first gate conductor in direct contact with a first gate dielectric, and wherein said first rate conductor comprises a low-temperature metal; and a p-channel transistor comprising a second gate structure arranged above said n-type active region, wherein said second gate structure comprises a second gate conductor over a second gate dielectric, and wherein said second gate conductor comprises a low-temperature metal, and wherein a composition of said second gate structure is different than a composition of said first gate structure.
Claim 3
Dependent Claim
29 words
The integrated circuit as recited in claim 1 , wherein a dielectric constant of said first gate dielectric is larger than a dielectric constant of said second gate dielectric.
Claim 4
Dependent Claim
19 words
The integrated circuit as recited in claim 1 , wherein said second gate conductor comprises a diffusion barrier layer.
Claim 5
Dependent Claim
18 words
The integrated circuit as recited in claim 3 , wherein said diffusion barrier layer comprises a metal nitride.
Claim 6
Dependent Claim
16 words
The integrated circuit as recited in claim 4 , wherein said metal nitride comprises titanium nitride.
Claim 7
Dependent Claim
27 words
The integrated circuit as recited in claim 1 , wherein a thickness of said first gate dielectric is smaller than a thickness of said second gate dielectric.
Claim 8
Dependent Claim
55 words
The integrated circuit as recited in claim 1 , wherein a work function of said first gate conductor is different than a work function of said second gate conductor, such that a magnitude of a threshold voltage of said p-channel transistor is approximately equal to a magnitude of a threshold voltage of said n-channel transistor.
Claim 9
Dependent Claim
23 words
The integrated circuit as recited in claim 1 , wherein said low-temperature metal comprises aluminum, an aluminum alloy, copper, or a copper alloy.
Claim 10
Dependent Claim
29 words
The integrated circuit as recited in claim 1 , wherein a lateral length of said first gate structure is smaller than a lateral length of said second gate structure.
Claim 11
Dependent Claim
146 words
An integrated circuit, comprising: an n-type active region of a semiconductor substrate separated from a p-type active region of said substrate by an isolation region; an n-channel transistor comprising a first gate structure arranged above said p-type active region, wherein said first gate structure comprises a first gate conductor over a first gate dielectric; and a p-channel transistor comprising a second gate structure arranged above said n-type active region, wherein said second gate structure comprises a second gate conductor over a second gate dielectric, and wherein said second gate conductor comprises a diffusion barrier layer interposed between said second gate conductor and said second gate dielectric, and wherein a composition of said second gate structure is different than a composition of said first gate structure, and wherein a lateral length of said first gate structure is smaller than a lateral length of said second gate structure.
Claim 12
Dependent Claim
146 words
An integrated circuit, comprising: an n-type active region of a semiconductor substrate separated from a p-type active region of said substrate by an isolation region; an n-channel transistor comprising a first gate structure arranged above said p-type active region, wherein said first gate structure comprises a first gate conductor over a first gate dielectric; and a p-channel transistor comprising a second gate structure arranged above said n-type active region, wherein said second gate structure comprises a second gate conductor over a second gate dielectric, and wherein said second gate conductor comprises a diffusion barrier layer interposed between said second gate conductor and said second gate dielectric, and wherein a composition of said second gate structure is different than a composition of said first gate structure, and wherein a lateral length of said first gate structure is smaller than a lateral length of said second gate structure.
Claim 13
Dependent Claim
55 words
The integrated circuit as recited in claim 10 , wherein a work function of said first gate conductor is different than a work function of said second gate conductor, such that a magnitude of a threshold voltage of said p-channel transistor is approximately equal to a magnitude of a threshold voltage of said n-channel transistor.
Claim 14
Dependent Claim
29 words
The integrated circuit as recited in claim 10 , wherein a dielectric constant of said first gate dielectric is larger than a dielectric constant of said second gate dielectric.
Claim 15
Dependent Claim
21 words
The integrated circuit as recited in claim 10 , wherein said first and said second gate conductors consist essentially of metal.
Claim 16
Dependent Claim
123 words
An integrated circuit, comprising: an n-type active region of a semiconductor substrate separated from a p-type active region of said substrate by an isolation region; an n-channel transistor comprising a first gate structure arranged above said p-type active region, wherein said first gate conductor comprises a first gate conductor over a first gate dielectric; and a p-channel transistor comprising a second gate structure arranged above said n-type active region, wherein second gate structure comprises a second gate conductor over a second gate dielectric, and wherein a dielectric constant of said second gate dielectric is smaller than a dielectric constant of said first gate dielectric, and wherein a composition of said second gate structure is different than a composition of said first gate structure.
Claim 17
Dependent Claim
123 words
An integrated circuit, comprising: an n-type active region of a semiconductor substrate separated from a p-type active region of said substrate by an isolation region; an n-channel transistor comprising a first gate structure arranged above said p-type active region, wherein said first gate conductor comprises a first gate conductor over a first gate dielectric; and a p-channel transistor comprising a second gate structure arranged above said n-type active region, wherein second gate structure comprises a second gate conductor over a second gate dielectric, and wherein a dielectric constant of said second gate dielectric is smaller than a dielectric constant of said first gate dielectric, and wherein a composition of said second gate structure is different than a composition of said first gate structure.
Claim 18
Dependent Claim
55 words
The integrated circuit as recited in claim 14 , wherein a work function of said first gate conductor is different than a work function of said second gate conductor, such that a magnitude of a threshold voltage of said p-channel transistor is approximately equal to a magnitude of a threshold voltage of said n-channel transistor.
Claim 19
Dependent Claim
21 words
The integrated circuit as recited in claim 14 , wherein said first and said second gate conductors consist essentially of metal.
Claim 20
Dependent Claim
19 words
The integrated circuit as recited in claim 14 , wherein said second gate conductor comprises a diffusion barrier layer.
Claim 21
Dependent Claim
29 words
The integrated circuit as recited in claim 14 , wherein a lateral length of said first gate structure is smaller than a lateral length of said second gate structure.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-02 | 2005-01-01 | 2005-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-02 | 2009-01-01 | 2009-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-02 | 2013-01-01 | 2013-07-03 | $7700.00 | Window Closed / Lapsed |