US5567642A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating gate electrode of CMOS device
Assignee: SK Hynix Inc
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Filing: 1995-11-06
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Granted: 1996-10-22
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Expires: 2015-11-06
Abstract
Abstract A method of fabricating a gate electrode of a CMOS device is disclosed including the steps of: sequentially forming a gate insulating layer, first conductive layer and protective layer on a semiconductor substrate; selectively etching a predetermined portion of the protective layer in which a PMOS transistor will be formed; forming a second conductive layer on the overall surface of said substrate; removing the second conductive layer formed on the protective layer, and partially etching the protective layer to a predetermined thickness; and patterning the second conductive layer, the protective layer, the first conductive layer and the gate insulating layer using a gate electrode pattern.
Inventors
- 👤 Hyeon S. Kim
- 👤 Choong H. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:52
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0177; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; H10P; H10P14/00; H10P14/40; H10P14/416; Y; Y10; Y10S; Y10S148/00; Y10S148/019
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
103 words
A method of fabricating a gate electrode of a CMOS device, comprising the steps of: sequentially forming a gate insulating layer, a first conductive layer and a protective layer on a semiconductor substrate; selectively etching a portion of said protective layer in which a PMOS transistor is formed; forming a second conductive layer on a resulting surface of said substrate; removing said second conductive layer formed on said protective layer, and partially etching said protective layer to a first thickness; and patterning said second conductive layer, said protective layer, said first conductive layer and said gate insulating layer to form a gate electrode.
Claim 2
Independent Claim
103 words
A method of fabricating a gate electrode of a CMOS device, comprising the steps of: sequentially forming a gate insulating layer, a first conductive layer and a protective layer on a semiconductor substrate; selectively etching a portion of said protective layer in which a PMOS transistor is formed; forming a second conductive layer on a resulting surface of said substrate; removing said second conductive layer formed on said protective layer, and partially etching said protective layer to a first thickness; and patterning said second conductive layer, said protective layer, said first conductive layer and said gate insulating layer to form a gate electrode.
Claim 3
Dependent Claim
25 words
The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, wherein said first conductive layer is formed of polysilicon.
Claim 4
Dependent Claim
25 words
The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, wherein said second conductive layer is formed of silicide.
Claim 5
Dependent Claim
47 words
The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, after the step of selectively etching a portion of said protective layer, further comprising the step of: partially etching an exposed portion of said first conductive layer to a second thickness.
Claim 6
Dependent Claim
43 words
The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, wherein said protective layer is partially removed to a first thickness so as to make surface heights of said protective layer and said second conductive layer same.
Claim 7
Dependent Claim
49 words
The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, after the step of partially etching said protective layer to a first determined thickness, further comprising the step of: ion-implanting a V-group impurity and III-group impurity into NMOS and PMOS transistor regions, respectively.
Claim 8
Dependent Claim
28 words
The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, wherein said protective layer is formed thicker than said second conductive layer.
Claim 9
Dependent Claim
35 words
The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, wherein said second conductive layer formed on said protective layer and said protective layer are removed using an etchant.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-22 | 2000-04-22 | 2000-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-22 | 2004-04-22 | 2004-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-22 | 2008-04-22 | 2008-10-22 | $7700.00 | Window Closed / Lapsed |