US6406945B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming a transistor gate dielectric with high-K and low-K regions
Assignee: GlobalFoundries Singapore Pte Ltd
•
Filing: 2001-01-26
•
Granted: 2002-06-18
•
Expires: 2021-01-26
Abstract
Abstract A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.
Inventors
- 👤 James Yong Meng Lee
- 👤 Ying Keung Leung
- 👤 Yelehanka Ramachandramurthy Pradeep
- 👤 Jia Zhen Zheng
- 👤 Lap Chan
- 👤 Elgin Quek
- 👤 Ravi Sundaresan
- 👤 Yang Pan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:48
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/691; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D64/681; H10D64/683; H10D64/693; H10D64/01342; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
123 words
A method for forming a transistor gate dielectric, comprising the steps of: a. forming a dummy layer over a semiconductor structure, and patterning said dummy layer to form a gate opening; wherein the bottom of said gate opening is the top surface of said semiconductor structure; b. forming a high-K dielectric layer on the bottom and sidewalls of said dummy dielectric layer, and forming a low-K dielectric layer on said high-K dielectric layer; c. forming spacers on the sidewalls of said gate opening; d. etching said low-K dielectric layer where it is not covered by said spacers; e. removing said spacers; and f. forming a gate electrode on and/or over said high-K dielectric layer and said low-K dielectric layer in said gate opening.
Claim 2
Independent Claim
123 words
A method for forming a transistor gate dielectric, comprising the steps of: a. forming a dummy layer over a semiconductor structure, and patterning said dummy layer to form a gate opening; wherein the bottom of said gate opening is the top surface of said semiconductor structure; b. forming a high-K dielectric layer on the bottom and sidewalls of said dummy dielectric layer, and forming a low-K dielectric layer on said high-K dielectric layer; c. forming spacers on the sidewalls of said gate opening; d. etching said low-K dielectric layer where it is not covered by said spacers; e. removing said spacers; and f. forming a gate electrode on and/or over said high-K dielectric layer and said low-K dielectric layer in said gate opening.
Claim 3
Dependent Claim
14 words
The method of claim 1 wherein said low-K dielectric layer comprises fluorinated silicon dioxide.
Claim 4
Dependent Claim
13 words
The method of claim 1 wherein said high-K dielectric comprises ZrO 2 .
Claim 5
Dependent Claim
15 words
The method of claim 1 wherein said high-K dielectric comprises Ta 2 O 5 .
Claim 6
Dependent Claim
13 words
The method of claim 1 wherein said high-K dielectric comprises TiO 2 .
Claim 7
Dependent Claim
15 words
The method of claim 1 wherein said high-K dielectric comprises Si 3 N 4 .
Claim 8
Dependent Claim
36 words
The method of claim 1 wherein said low-K dielectric layer has a thickness of between about 30 angstroms and 100 angstroms and said high-K dielectric has a thickness of between about 10 angstroms and 100 angstroms.
Claim 9
Dependent Claim
32 words
The method of claim 1 wherein said low-K dielectric layer extends under the gate electrode a distance of between about 50 angstroms and 200 angstroms at each edge of the gate electrode.
Claim 10
Dependent Claim
71 words
The method of claim 1 which further comprise the steps of: (g) planarizing said gate-electrode, said low-K dielectric layer; and said high-K dielectric layer stopping on said dummy layer; (h) removing said dummy layer; (i) forming lightly doped source and drain regions in said semiconductor structure adjacent said gate electrode; (j) forming spacers adjacent said gate electrode; and (k) forming source and drain regions in said semiconductor structure adjacent said spacers.
Claim 11
Dependent Claim
21 words
The method of claim 9 wherein said low-K dielectric extends over at least a portion of said lightly doped source/drain regions.
Claim 12
Independent Claim
209 words
A method for forming a transistor gate dielectric, comprising the steps of: a. forming a dummy layer over a semiconductor structure, and patterning said dummy layer to form a gate opening; wherein the bottom of said gate opening is the top surface of said semiconductor structure; b. forming a high-K dielectric layer on the bottom and sidewalls of said dummy layer, and forming a low-K dielectric layer on said high-K dielectric layer; c. forming spacers on the sidewalls of said gate opening; d. etching said low-K dielectric layer where it is not covered by said spacers; e. removing said spacers; f. forming a gate electrode on and/or over said high-K dielectric layer and said low-K dielectric layer in said gate opening; wherein said low-K dielectric layer extends under the gate electrode a distance of between about 50 angstroms and 200 angstroms at each edge of the gate electrode; (g) planarizing said gate electrode, said low-K dielectric layer, and said high-K dielectric layer stopping on said dummy layer; (h) removing said dummy layer; (i) forming lightly doped source and drain regions in said semiconductor structure adjacent said gate electrode; (l) forming spacers adjacent said gate electrode; and (k) forming source and drain regions in said semiconductor structure adjacent said spacers.
Claim 13
Independent Claim
209 words
A method for forming a transistor gate dielectric, comprising the steps of: a. forming a dummy layer over a semiconductor structure, and patterning said dummy layer to form a gate opening; wherein the bottom of said gate opening is the top surface of said semiconductor structure; b. forming a high-K dielectric layer on the bottom and sidewalls of said dummy layer, and forming a low-K dielectric layer on said high-K dielectric layer; c. forming spacers on the sidewalls of said gate opening; d. etching said low-K dielectric layer where it is not covered by said spacers; e. removing said spacers; f. forming a gate electrode on and/or over said high-K dielectric layer and said low-K dielectric layer in said gate opening; wherein said low-K dielectric layer extends under the gate electrode a distance of between about 50 angstroms and 200 angstroms at each edge of the gate electrode; (g) planarizing said gate electrode, said low-K dielectric layer, and said high-K dielectric layer stopping on said dummy layer; (h) removing said dummy layer; (i) forming lightly doped source and drain regions in said semiconductor structure adjacent said gate electrode; (l) forming spacers adjacent said gate electrode; and (k) forming source and drain regions in said semiconductor structure adjacent said spacers.
Claim 14
Dependent Claim
14 words
The method of claim 11 wherein said low-K dielectric layer comprises fluorinated silicon dioxide.
Claim 15
Dependent Claim
13 words
The method of claim 11 wherein said high-K dielectric comprises ZrO 2 .
Claim 16
Dependent Claim
15 words
The method of claim 11 wherein said high-K dielectric comprises Ta 2 O 5 .
Claim 17
Dependent Claim
13 words
The method of claim 11 wherein said high-K dielectric comprises TiO 2 .
Claim 18
Dependent Claim
15 words
The method of claim 11 wherein said high-K dielectric comprises Si 3 N 4 .
Claim 19
Dependent Claim
36 words
The method of claim 11 wherein said low-K dielectric layer has a thickness of between about 30 angstroms and 100 angstroms and said high-K dielectric has a thickness of between about 10 angstroms and 100 angstroms.
References Cited (Backward Citations)
US5736435A
Cited
US5882971A
Cited
US5952700A
Cited
US6163060A
Cited
US6271132B1
Cited
US6242776B1
Cited
US6255703B1
Cited
US6351013B1
Cited
US6284580B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-06-17 | 2005-12-17 | 2006-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-17 | 2009-12-17 | 2010-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-17 | 2013-12-17 | 2014-06-18 | $7700.00 | Window Closed / Lapsed |