Patent US4098389A successfully refreshed from Google Patents.
Patent US6738601B1 successfully refreshed from Google Patents.
US6738601B1
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US
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Adaptive radio transceiver with floating MOSFET capacitors
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2000-10-18
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Granted: 2004-05-18
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Expires: 2020-10-18
Abstract
Abstract An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
Inventors
- 👤 Ahmadreza Rofougaran
- 👤 Maryam Rofougaran
- 👤 Shahla Khorram
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:35
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03B; H03B21/00; H03B21/01; H03B27/00; H03F; H03F1/00; H03F1/56; H03F3/00; H03F3/189; H03F3/19; H03F3/20; H03F3/24; H03F3/245; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/45475; H03G; H03G11/00; H03G3/00; H03G3/001; H03H; H03H11/00; H03H11/02; H03H11/04; H03H11/12; H03H11/126; H03H11/1291; H03H11/16; H03H11/22; H03H11/34; H03H11/344; H03H21/00; H03H21/0001; H03H21/0012; H03H7/00; H03H7/42; H03L7/08; H03L7/099; H04; H04B; H04B17/00; H04B17/10; H04B17/101; H04B17/104; H04B17/11; H04B17/14; H04B17/15; H04B17/19; H03F2200/00; H03F2200/318; H03F2200/336; H03F2200/451; H03F2203/00; H03F2203/45; H03F2203/45138; H03F2203/45386; H03F2203/45526; H03F2203/45528; H03F2203/45638; H03H2011/0494; H03H2210/00; H03H2210/02; H03H2210/025; H03H2210/03; H03H2210/036; H03J; H03J2200/00; H03J2200/10
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
110 words
A capacitor comprising: a first node for receiving a signal; a first transistor comprising a gate node and at least one other node, the at least one other node coupled to receive the signal from the first node; a second transistor comprising a gate node and at least one other node, the gate node of the second transistor coupled to receive the signal from the gate node of the first transistor; and a second node coupled to receive the signal from the at least one other node of the second transistor; wherein the first transistor and the second transistor provide a capacitance between the first node and the second node.
Claim 2
Dependent Claim
110 words
A capacitor comprising: a first node for receiving a signal; a first transistor comprising a gate node and at least one other node, the at least one other node coupled to receive the signal from the first node; a second transistor comprising a gate node and at least one other node, the gate node of the second transistor coupled to receive the signal from the gate node of the first transistor; and a second node coupled to receive the signal from the at least one other node of the second transistor; wherein the first transistor and the second transistor provide a capacitance between the first node and the second node.
Claim 3
Dependent Claim
18 words
The capacitor of claim 1 wherein the first and second transistors each comprises a metal oxide semiconductor (MOS).
Claim 4
Dependent Claim
12 words
The capacitor of claim 2 wherein the capacitor is a floating capacitor.
Claim 5
Dependent Claim
57 words
The capacitor of claim 3 wherein each of the at least one other node of the first and second transistors comprises a, drain and a source, the drain and the source of the first transistor being coupled to the first node, and the drain and the source of the second transistor being coupled to the second node.
Claim 6
Dependent Claim
21 words
The capacitor of claim 2 further comprising a bias resistor coupled to the gate nodes of the first and second transistors.
Claim 7
Dependent Claim
57 words
The capacitor of claim 2 wherein each of the at least one other node of the first and second transistors comprises a drain and a source, the drain and the source of the first transistor being coupled to the first node and the drain and the source of the second transistor being coupled to the second node.
Claim 8
Dependent Claim
21 words
The capacitor of claim 6 further comprising a bias resistor coupled to the gate nodes of the first and second transistors.
Claim 9
Dependent Claim
111 words
An integrated circuit comprising: a first node for receiving a signal; a first transistor comprising a gate node and at least one other node, the at least one other node coupled to receive the signal from the first node; a second transistor comprising a gate node and at least one other node, the gate node of the second transistor coupled to receive the signal from the gate node of the first transistor; and a second node coupled to receive the signal from the at least one other node of the second transistor; wherein the first transistor and the second transistor provide a capacitance between the first node and the second node.
Claim 10
Dependent Claim
111 words
An integrated circuit comprising: a first node for receiving a signal; a first transistor comprising a gate node and at least one other node, the at least one other node coupled to receive the signal from the first node; a second transistor comprising a gate node and at least one other node, the gate node of the second transistor coupled to receive the signal from the gate node of the first transistor; and a second node coupled to receive the signal from the at least one other node of the second transistor; wherein the first transistor and the second transistor provide a capacitance between the first node and the second node.
Claim 11
Dependent Claim
19 words
The integrated circuit of claim 8 wherein the first and second transistors each comprises a metal oxide semiconductor (MOS).
Claim 12
Dependent Claim
14 words
The integrated circuit of claim 9 wherein the integrated circuit comprises a floating capacitor.
Claim 13
Dependent Claim
58 words
The integrated circuit of claim 10 wherein each of the at least one other node of the first and second transistors comprises a drain and a source, the drain and the source of the first transistor being coupled to the first node, and the drain and the source of the second transistor being coupled to the second node.
Claim 14
Dependent Claim
22 words
The integrated circuit of claim 9 further comprising a bias resistor coupled to the gate nodes of the first and second transistors.
Claim 15
Dependent Claim
58 words
The integrated circuit of claim 9 wherein each of the at least one other node of the first and second transistors comprises a drain and a source, the drain and the source of the first transistor being coupled to the first node and the drain and the source of the second transistor being coupled to the second node.
Claim 16
Dependent Claim
22 words
The integrated circuit of claim 13 further comprising a bias resistor coupled to the gate nodes of the first and second transistors.
Claim 17
Dependent Claim
163 words
A tunable capacitor array, comprising: a plurality of capacitors each of the capacitors comprising: a first node for receiving a signal; a first transistor comprising a gate node and at least one other node, the at least one other node coupled to receive the signal from the first node; a second transistor comprising a gate node and at least one other node, the gate node of the second transistor coupled to receive the signal from the gate node of the first transistor; and a second node coupled to receive the signal from the at least one other node of the second transistor; wherein the first transistor and the second transistor provide a capacitance between the first node and the second node; the first nodes of the capacitors being coupled together and the second nodes of the capacitors being coupled together; and a plurality of switches each being positioned between a different one of the capacitors and the respective capacitors first or second node.
Claim 18
Dependent Claim
163 words
A tunable capacitor array, comprising: a plurality of capacitors each of the capacitors comprising: a first node for receiving a signal; a first transistor comprising a gate node and at least one other node, the at least one other node coupled to receive the signal from the first node; a second transistor comprising a gate node and at least one other node, the gate node of the second transistor coupled to receive the signal from the gate node of the first transistor; and a second node coupled to receive the signal from the at least one other node of the second transistor; wherein the first transistor and the second transistor provide a capacitance between the first node and the second node; the first nodes of the capacitors being coupled together and the second nodes of the capacitors being coupled together; and a plurality of switches each being positioned between a different one of the capacitors and the respective capacitors first or second node.
Claim 19
Dependent Claim
25 words
The tunable capacitor array of claim 15 wherein the first and second transistors for each of the capacitors each comprises a metal oxide semiconductor (MOS).
Claim 20
Dependent Claim
13 words
The tunable capacitor array of claim 16 wherein the capacitors comprise floating capacitors.
Claim 21
Dependent Claim
66 words
The tunable capacitor array of claim 17 wherein each of the at least one other node of the first and second transistors for each of the capacitors comprises a drain and a source, the drain and the source of the first transistors each being coupled to the first nodes, and the drain and the source of the second transistors each being coupled to the second nodes.
Claim 22
Dependent Claim
28 words
The tunable capacitor array of claim 16 wherein the capacitors each comprises a bias resistor coupled to the gate nodes of the respective capacitors first and second transistors.
Claim 23
Dependent Claim
66 words
The tunable capacitor array of claim 16 wherein each of the at least one other node of the first and second transistors for each of the capacitors comprises a drain and a source, the drain and the source of the first transistors each being coupled to the first nodes, and the drain and the source of the second transistors each being coupled to the second nodes.
Claim 24
Dependent Claim
27 words
The tunable capacitor array of claim 20 wherein the capacitors each comprises a bias resistor coupled to the gate nodes of its respective first and second transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-05-18 | 2007-11-17 | 2008-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-05-18 | 2011-11-17 | 2012-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-05-18 | 2015-11-17 | 2016-05-18 | $7700.00 | Window Closed / Lapsed |