US6704794B1 — Cell reassembly for packet based networks

Claim 1

Independent Claim 160 words

An apparatus, comprising: a cell processing pipeline comprising a plurality of pipeline stages, said cell processing pipeline further comprising a pipeline stage to, within a pipeline cycle, 1) parse a payload of a cell if said cell payload carries a portion of a packet's header and a portion of said packet's payload; 2) determine packet state information, where, whether or not a following cell that carries a next portion of said packet carries a portion of said packet's header can be determined from said packet state information; said pipeline stage further comprising, to said parse and to said determine, a micro program sequencer and an execution unit coupled to said micro program sequencer, said pipeline stage coupled to a register, said register to provide said packet state information back to said pipeline stage if a next cell to be evaluated for parsing by said pipeline stage within a next pipeline cycle after said pipeline cycle is also said following cell.

Claim 2

Independent Claim 160 words

An apparatus, comprising: a cell processing pipeline comprising a plurality of pipeline stages, said cell processing pipeline further comprising a pipeline stage to, within a pipeline cycle, 1) parse a payload of a cell if said cell payload carries a portion of a packet's header and a portion of said packet's payload; 2) determine packet state information, where, whether or not a following cell that carries a next portion of said packet carries a portion of said packet's header can be determined from said packet state information; said pipeline stage further comprising, to said parse and to said determine, a micro program sequencer and an execution unit coupled to said micro program sequencer, said pipeline stage coupled to a register, said register to provide said packet state information back to said pipeline stage if a next cell to be evaluated for parsing by said pipeline stage within a next pipeline cycle after said pipeline cycle is also said following cell.

Claim 3

Dependent Claim 86 words

The apparatus of claim 1 further comprising first register space and second register space, said first register space to store information that identifies a connection over which said cell arrived, said second register space to store information that identifies a connection over which said next cell arrived, said register to provide said packet state information back to said pipeline stage if the contents of said first and second register spaces indicate the same connection so as to indicate said next cell is also said following cell.

Claim 4

Dependent Claim 46 words

The apparatus of claim 2 wherein said first register space is accessible to a first pipeline stage that precedes said pipeline stage in said pipeline, and wherein, said second register space is accessible to a third pipeline stage that follows said pipeline stage in said pipeline.

Claim 5

Dependent Claim 60 words

The apparatus of claim 3 wherein said first and third pipeline stages are coupled to a memory, said memory to store packet state information determined by said pipeline stage upon its being sent from said third pipeline stage, said memory to provide said packet state information to said first pipeline stage upon said following cell being presented to said pipeline.

Claim 6

Dependent Claim 61 words

The apparatus of claim 4 wherein said memory is to further to store, along with said packet state information, said packet header portion parsed by said pipeline stage upon its being sent from said third pipeline stage, said memory to also provide said packet header portion to said first pipeline stage upon said following cell being said presented to said pipeline.

Claim 7

Dependent Claim 40 words

The apparatus of claim 5 further comprising a second memory coupled to said first stage, said second memory to provide said information that identifies a connection over which said cell arrived in response to a parameter associated with said cell.

Claim 8

Dependent Claim 12 words

The apparatus of claim 6 wherein said parameter is said cell's VPI/VCI.

Claim 9

Dependent Claim 15 words

The apparatus of claim 7 wherein said second memory is a content addressable memory (CAM).

Claim 10

Dependent Claim 85 words

The apparatus of claim 1 further comprising a first pipeline stage that precedes said pipeline stage in said pipeline and a third pipeline stage that follows said pipeline stage in said pipeline, said first and third pipeline stages coupled to a memory, said memory to store packet state information determined by said pipeline stage upon its being sent from said third pipeline stage, said memory to provide said packet state information to said first pipeline stage upon said following cell being presented to said pipeline.

Claim 11

Dependent Claim 61 words

The apparatus of claim 9 wherein said memory is to further to store, along with said packet state information, said packet header portion parsed by said pipeline stage upon its being sent from said third pipeline stage, said memory to also provide said packet header portion to said first pipeline stage upon said following cell being said presented to said pipeline.

Claim 12

Dependent Claim 39 words

The apparatus of claim 9 further comprising a second memory coupled to said first stage, said second memory to provide information that identifies a connection over which said cell arrived in response to a parameter associated with said cell.

Claim 13

Dependent Claim 11 words

The apparatus of claim 11 said parameter is said cell's VPI/VCI.

Claim 14

Dependent Claim 15 words

The apparatus of claim 11 wherein said second memory is a content addressable memory (CAM).

Claim 15

Dependent Claim 31 words

The apparatus of claim 1 wherein said packet state information includes a cell count that tracks how many cells of said packet have been evaluated for parsing by said pipeline stage.

Claim 16

Dependent Claim 27 words

The apparatus of claim 1 further comprising a micro-program memory coupled to said sequencer, said micro-program memory to store micro-programs that are executable by said pipeline stage.

Claim 17

Dependent Claim 31 words

The apparatus of claim 15 wherein at least one of said micro-programs is to be executed by said pipeline stage for cells carrying a portion of a specific type of packet.

Claim 18

Dependent Claim 13 words

The apparatus of claim 16 wherein said specific type of packet is IP.

Claim 19

Dependent Claim 13 words

The apparatus of claim 16 wherein said specific type of packet is MPLS.

Claim 20

Dependent Claim 14 words

The apparatus of claim 16 wherein said specific type of packet is Frame Relay.

Claim 21

Dependent Claim 13 words

The apparatus of claim 16 wherein said specific type of packet is AAL0.

Claim 22

Dependent Claim 13 words

The apparatus of claim 16 wherein said specific type of packet is AAL5.

Claim 23

Dependent Claim 15 words

The apparatus of claim 16 wherein said specific type of packet is Packet Over SONET.

Claim 24

Dependent Claim 42 words

The apparatus of claim 22 wherein said at least one of said micro-programs contains instructions sufficient for said pipeline stage to determine at least one of the following: a) a length indicator; b) a timestamp insert flag; c) a record route flag.

Claim 25

Dependent Claim 61 words

The apparatus of claim 1 wherein said pipeline stage further comprises an interface to a free space lists manager so that a pointer can be retrieved within said pipeline cycle, said pointer to point to a location in a packet buffer where payload information (if any) of said packet carried by said following cell will be written into said packet buffer.

Claim 26

Dependent Claim 34 words

The apparatus of claim 24 further comprising register space accessible to said pipeline stage to which said pipeline stage provides said pointer, said packet state information and any parsed portion of said packet's header.

Claim 27

Dependent Claim 56 words

The apparatus of claim 24 wherein said pipeline further comprises a following pipeline stage relative to said pipeline stage, said following pipeline stage coupled to said packet buffer so that said packet payload information (if any) carried by said following cell can be written to said location in said packet buffer pointed to by said pointer.

Claim 28

Dependent Claim 71 words

The apparatus of claim 26 further comprising another pipeline stage that precedes said pipeline stage in said pipeline, said following and another pipeline stages coupled to a memory, said memory to store packet state information determined by said pipeline stage upon its being sent from said following pipeline stage, said memory to provide said packet state information to said another pipeline stage upon said following cell being presented to said pipeline.

Claim 29

Dependent Claim 17 words

The apparatus of claim 1 wherein said pipeline stage does not said parse for Layer 2 flows.

Claim 30

Independent Claim 131 words

A method, comprising: a) within a first cycle of a pipeline: parsing a cell payload if said cell payload carries a portion of a packet's header and a portion of said packet's payload; determining packet state information for said packet, where, whether or not a following cell that carries a next portion of said packet carries a portion of said packet's header can be determined from said packet state information; and, b) within a second cycle of said pipeline that immediately follows said first cycle and as a consequence of recognizing that a next cell that immediately follows said cell in the processing sequences of said pipeline is said following cell: using said packet state information to determine whether or not said next cell carries a portion of said packet's header.

Claim 31

Independent Claim 131 words

A method, comprising: a) within a first cycle of a pipeline: parsing a cell payload if said cell payload carries a portion of a packet's header and a portion of said packet's payload; determining packet state information for said packet, where, whether or not a following cell that carries a next portion of said packet carries a portion of said packet's header can be determined from said packet state information; and, b) within a second cycle of said pipeline that immediately follows said first cycle and as a consequence of recognizing that a next cell that immediately follows said cell in the processing sequences of said pipeline is said following cell: using said packet state information to determine whether or not said next cell carries a portion of said packet's header.

Claim 32

Dependent Claim 21 words

The method of claim 29 further comprising within said first cycle: looking up a connection that said next cell arrived on.

Claim 33

Dependent Claim 23 words

The method of claim 30 wherein an input parameter for said looking up employs at least a portion of said next cell's header.

Claim 34

Dependent Claim 23 words

The method of claim 30 wherein said recognizing further comprises recognizing that said connection is the same connection that said cell arrived on.

Claim 35

Dependent Claim 23 words

The method of claim 29 further comprising executing a micro program to perform said parsing and said determining within said first pipeline cycle.

Claim 36

Dependent Claim 18 words

The method of claim 33 wherein said micro program is specific to the specific type of said packet.

Claim 37

Dependent Claim 13 words

The method of claim 34 wherein said specific type of packet is IP.

Claim 38

Dependent Claim 13 words

The method of claim 34 wherein said specific type of packet is MPLS.

Claim 39

Dependent Claim 14 words

The method of claim 34 wherein said specific type of packet is Frame Relay.

Claim 40

Dependent Claim 13 words

The method of claim 34 wherein said specific type of packet is AAL0.

Claim 41

Dependent Claim 13 words

The method of claim 34 wherein said specific type of packet is AAL5.

Claim 42

Dependent Claim 15 words

The method of claim 34 wherein said specific type of packet is Packet Over SONET.

Claim 43

Dependent Claim 37 words

The method of claim 29 further comprising retrieving, within said first pipeline cycle, a pointer that identifies where payload information (if any) of said packet carried by said following cell will be written into a buffer memory.

Claim 44

Dependent Claim 27 words

The method of claim 41 further comprising writing payload information of said packet carried by said following cell into said buffer memory after said second pipeline cycle.

Claim 45

Dependent Claim 22 words

The method of claim 42 further comprising performing said writing during a third pipeline cycle that immediately follows said second pipeline cycle.

Claim 46

Dependent Claim 49 words

The method of claim 43 further comprising, during said second pipeline cycle, updating said packet state information for said packet, so that, it can be determined whether or not a second following cell that carries a second next portion of said packet carries a portion of said packet's header.

Claim 47

Dependent Claim 21 words

The method of claim 44 further comprising writing said updated packet state information into a memory during said third pipeline cycle.

Claim 48

Dependent Claim 38 words

The method of claim 45 further comprising looking up said updated packet state information with a term associated with said second following cell as a consequence of said second following cell being presented to said pipeline for processing.

Claim 49

Dependent Claim 15 words

The method of claim 46 where said term at least includes said cell's VPI/VCI information.

Claim 50

Dependent Claim 49 words

The method of claim 29 further comprising, during said second pipeline cycle, updating said packet state information for said packet, so that, it can be determined whether or not a second following cell that carries a second next portion of said packet carries a portion of said packet's header.

Claim 51

Dependent Claim 21 words

The method of claim 48 further comprising writing said updated packet state information into a memory during said third pipeline cycle.

Claim 52

Dependent Claim 38 words

The method of claim 49 further comprising looking up said updated packet state information with a term associated with said second following cell as a consequence of said second following cell being presented to said pipeline for processing.

Claim 53

Dependent Claim 15 words

The method of claim 50 where said term at least includes said cell's VPI/VCI information.

Claim 54

Independent Claim 129 words

An apparatus, comprising: a) means for, within a first cycle, parsing a cell payload if said cell payload carries a portion of a packet's header and a portion of said packet's payload; determining packet state information for said packet, where, whether or not a following cell that carries a next portion of said packet carries a portion of said packet's header can be determined from said packet state information; and, b) means for, within a second cycle that immediately follows said first cycle and as a consequence of recognizing that a next cell that immediately follows said cell in a series of pipelined processing sequences is said following cell, using said packet state information to determine whether or not said next cell carries a portion of said packet's header.

Claim 55

Independent Claim 129 words

An apparatus, comprising: a) means for, within a first cycle, parsing a cell payload if said cell payload carries a portion of a packet's header and a portion of said packet's payload; determining packet state information for said packet, where, whether or not a following cell that carries a next portion of said packet carries a portion of said packet's header can be determined from said packet state information; and, b) means for, within a second cycle that immediately follows said first cycle and as a consequence of recognizing that a next cell that immediately follows said cell in a series of pipelined processing sequences is said following cell, using said packet state information to determine whether or not said next cell carries a portion of said packet's header.

Claim 56

Dependent Claim 23 words

The apparatus of claim 52 further comprising means for, within said first cycle, looking up a connection that said next cell arrived on.

Claim 57

Dependent Claim 38 words

The apparatus of claim 52 further comprising means for retrieving, within said first cycle, a pointer that identifies where payload information (if any) of said packet carried by said following cell will be written into a buffer memory.

Claim 58

Dependent Claim 28 words

The apparatus of claim 52 further comprising means for writing said updated packet state information into a memory during a third cycle that immediately follows said second cycle.

Claim 59

Dependent Claim 50 words

The apparatus of claim 52 further comprising means for, during said second cycle, updating said packet state information for said packet, so that, it can be determined whether or not a second following cell that carries a second next portion of said packet carries a portion of said packet's header.

Claim 60

Dependent Claim 28 words

The apparatus of claim 56 further comprising means for writing said updated packet state information into a memory during a third cycle that immediately follows said second cycle.

Claim 61

Dependent Claim 174 words

A machine readable medium containing a description of a design for a semiconductor circuit, said circuit comprising: a cell processing pipeline comprising a plurality of pipeline stages, said cell processing pipeline further comprising a pipeline stage to, within a pipeline cycle, 1) parse a payload of a cell if said cell payload carries a portion of a packet's header and a portion of said packet's payload; 2) determine packet state information, where, whether or not a following cell that carries a next portion of said packet carries a portion of said packet's header can be determined from said packet state information; said pipeline stage further comprising, to said parse and to said determine, a micro program sequencer and an execution unit coupled to said micro program sequencer, said pipeline stage coupled to a register, said register to provide said packet state information back to said pipeline stage if a next cell to be evaluated for parsing by said pipeline stage within a next pipeline cycle after said pipeline cycle is also said following cell.

Claim 62

Dependent Claim 174 words

A machine readable medium containing a description of a design for a semiconductor circuit, said circuit comprising: a cell processing pipeline comprising a plurality of pipeline stages, said cell processing pipeline further comprising a pipeline stage to, within a pipeline cycle, 1) parse a payload of a cell if said cell payload carries a portion of a packet's header and a portion of said packet's payload; 2) determine packet state information, where, whether or not a following cell that carries a next portion of said packet carries a portion of said packet's header can be determined from said packet state information; said pipeline stage further comprising, to said parse and to said determine, a micro program sequencer and an execution unit coupled to said micro program sequencer, said pipeline stage coupled to a register, said register to provide said packet state information back to said pipeline stage if a next cell to be evaluated for parsing by said pipeline stage within a next pipeline cycle after said pipeline cycle is also said following cell.

Claim 63

Dependent Claim 91 words

The machine readable medium of claim 58 wherein said circuit further comprises first register space and second register space, said first register space to store information that identifies a connection over which said cell arrived, said second register space to store information that identifies a connection over which said next cell arrived, said register to provide said packet state information back to said pipeline stage if the contents of said first and second register spaces indicate the same connection so as to indicate said next cell is also said following cell.

Claim 64

Dependent Claim 48 words

The machine readable medium of claim 59 wherein said first register space is accessible to a first pipeline stage that precedes said pipeline stage in said pipeline, and wherein, said second register space is accessible to a third pipeline stage that follows said pipeline stage in said pipeline.

Claim 65

Dependent Claim 15 words

The machine readable medium of claim 58 of wherein said circuit is described in VHDL.

Claim 66

Dependent Claim 18 words

The machine readable medium of claim 58 wherein said circuit is described at a Register Transfer Level (RTL).

Claim 67

Dependent Claim 174 words

A networking system, comprising: a packet aggregation layer to perform cell reassembly, said packet aggregation layer comprising: a cell processing pipeline comprising a plurality of pipeline stages, said cell processing pipeline further comprising a pipeline stage to, within a pipeline cycle, 1) parse a payload of a cell if said cell payload carries a portion of a packet's header and a portion of said packet's payload; 2) determine packet state information, where, whether or not a following cell that carries a next portion of said packet carries a portion of said packet's header can be determined from said packet state information; said pipeline stage further comprising, to said parse and to said determine, a micro program sequencer and an execution unit coupled to said micro program sequencer, said pipeline stage coupled to a register, said register to provide said packet state information back to said pipeline stage if a next cell to be evaluated for parsing by said pipeline stage within a next pipeline cycle after said pipeline cycle is also said following cell.

Claim 68

Dependent Claim 174 words

A networking system, comprising: a packet aggregation layer to perform cell reassembly, said packet aggregation layer comprising: a cell processing pipeline comprising a plurality of pipeline stages, said cell processing pipeline further comprising a pipeline stage to, within a pipeline cycle, 1) parse a payload of a cell if said cell payload carries a portion of a packet's header and a portion of said packet's payload; 2) determine packet state information, where, whether or not a following cell that carries a next portion of said packet carries a portion of said packet's header can be determined from said packet state information; said pipeline stage further comprising, to said parse and to said determine, a micro program sequencer and an execution unit coupled to said micro program sequencer, said pipeline stage coupled to a register, said register to provide said packet state information back to said pipeline stage if a next cell to be evaluated for parsing by said pipeline stage within a next pipeline cycle after said pipeline cycle is also said following cell.

Claim 69

Dependent Claim 92 words

The networking system of claim 63 wherein said packet aggregation layer further comprises first register space and second register space, said first register space to store information that identifies a connection over which said cell arrived, said second register space to store information that identifies a connection over which said next cell arrived, said register to provide said packet state information back to said pipeline stage if the contents of said first and second register spaces indicate the same connection so as to indicate said next cell is also said following cell.

Claim 70

Dependent Claim 47 words

The networking system of claim 64 wherein said first register space is accessible to a first pipeline stage that precedes said pipeline stage in said pipeline, and wherein, said second register space is accessible to a third pipeline stage that follows said pipeline stage in said pipeline.

Claim 71

Dependent Claim 61 words

The networking system of claim 65 wherein said first and third pipeline stages are coupled to a memory, said memory to store packet state information determined by said pipeline stage upon its being sent from said third pipeline stage, said memory to provide said packet state information to said first pipeline stage upon said following cell being presented to said pipeline.

Claim 72

Dependent Claim 62 words

The networking system of claim 66 wherein said memory is to further to store, along with said packet state information, said packet header portion parsed by said pipeline stage upon its being sent from said third pipeline stage, said memory to also provide said packet header portion to said first pipeline stage upon said following cell being said presented to said pipeline.

Claim 73

Dependent Claim 41 words

The networking system of claim 67 further comprising a second memory coupled to said first stage, said second memory to provide said information that identifies a connection over which said cell arrived in response to a parameter associated with said cell.

Claim 74

Dependent Claim 13 words

The networking system of claim 68 wherein said parameter is said cell's VPI/VCI.

Claim 75

Dependent Claim 16 words

The networking system of claim 69 wherein said second memory is a content addressable memory (CAM).

Claim 76

Dependent Claim 86 words

The networking system of claim 63 further comprising a first pipeline stage that precedes said pipeline stage in said pipeline and a third pipeline stage that follows said pipeline stage in said pipeline, said first and third pipeline stages coupled to a memory, said memory to store packet state information determined by said pipeline stage upon its being sent from said third pipeline stage, said memory to provide said packet state information to said first pipeline stage upon said following cell being presented to said pipeline.

Claim 77

Dependent Claim 62 words

The networking system of claim 71 wherein said memory is to further to store, along with said packet state information, said packet header portion parsed by said pipeline stage upon its being sent from said third pipeline stage, said memory to also provide said packet header portion to said first pipeline stage upon said following cell being said presented to said pipeline.

Claim 78

Dependent Claim 32 words

The networking system of claim 63 wherein said packet state information includes a cell count that tracks how many cells of said packet have been evaluated for parsing by said pipeline stage.

Claim 79

Dependent Claim 28 words

The networking system of claim 63 further comprising a micro-program memory coupled to said sequencer, said micro-program memory to store micro-programs that are executable by said pipeline stage.

Claim 80

Dependent Claim 32 words

The networking system of claim 74 wherein at least one of said micro-programs is to be executed by said pipeline stage for cells carrying a portion of a specific type of packet.

Claim 81

Dependent Claim 43 words

The networking system of claim 74 wherein said at least one of said micro-programs contains instructions sufficient for said pipeline stage to determine at least one of the following: a) a length indicator; b) a timestamp insert flag; c) a record route flag.

Claim 82

Dependent Claim 62 words

The networking system of claim 63 wherein said pipeline stage further comprises an interface to a free space lists manager so that a pointer can be retrieved within said pipeline cycle, said pointer to point to a location in a packet buffer where payload information (if any) of said packet carried by said following cell will be written into said packet buffer.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2007-03-09	2007-09-08	2008-03-09	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2011-03-09	2011-09-08	2012-03-09	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2015-03-09	2015-09-08	2016-03-09	$7700.00	Window Closed / Lapsed

Cell reassembly for packet based networks

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