Patent US6693004B1 successfully refreshed from Google Patents.
US6693004B1
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Interfacial barrier layer in semiconductor devices with high-K gate dielectric material
Assignee: GlobalFoundries US Inc
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Filing: 2002-02-27
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Granted: 2004-02-17
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Expires: 2022-02-27
Abstract
Abstract A semiconductor device and a process for fabricating the device, including, in one embodiment, a silicon substrate; a first interfacial barrier layer on the silicon substrate, in which the first interfacial barrier layer may include aluminum oxide, silicon nitride, silicon oxynitride or a mixture thereof; and a layer of a high-K dielectric material. The device may further include a second interfacial barrier layer on the high-K dielectric material layer, and may further include a polysilicon or polysilicon-germanium gate electrode formed on the second interfacial barrier layer.
Inventors
- 👤 Arvind Halliyal
- 👤 Joong S. Jeon
- 👤 Minh Van Ngo
- 👤 William G. En
- 👤 Effiong Ibok
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:18
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D64/01304; H10D64/01314; H10D64/031; H10D64/033; H10D64/035; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10D1/684; H10D64/037; H10D64/691; H10D64/693
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
215 words
A process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, comprising: depositing on the silicon substrate a first interfacial barrier layer of aluminum oxide, silicon nitride, silicon oxynitride or mixtures thereof; depositing on the interfacial barrier layer a layer comprising at least one high-K dielectric material, with the proviso that when the first interfacial barrier layer is silicon nitride, silicon oxynitride or mixtures thereof, the layer comprising at least one high-K dielectric material does not include a metal oxynitride, wherein the high-K dielectric material comprises at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), barium titanate (BaTiO 3 ), titanium dioxide (TiO 2 ), cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), lead titanate (PbTiO 3 ), silicon titanate (SrTiO 3 ), lead zirconate (PbZrO 3 ), tungsten oxide (WO 3 ), yttrium oxide (Y 2 O 3 ), bismuth silicon oxide (Bi 4 Si 2 O 12 ), barium strontium titanate (BST) (Ba 1−x Sr x TiO 3 ), PMN (PbMg x Nb 1−x O 3 ), PZT (PbZr x Ti 1−x O 3 ), PZN (PbZn x Nb 1−x O 3 ), and PST (PbSc x Ta 1−x O 3 ).
Claim 2
Dependent Claim
215 words
A process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, comprising: depositing on the silicon substrate a first interfacial barrier layer of aluminum oxide, silicon nitride, silicon oxynitride or mixtures thereof; depositing on the interfacial barrier layer a layer comprising at least one high-K dielectric material, with the proviso that when the first interfacial barrier layer is silicon nitride, silicon oxynitride or mixtures thereof, the layer comprising at least one high-K dielectric material does not include a metal oxynitride, wherein the high-K dielectric material comprises at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), barium titanate (BaTiO 3 ), titanium dioxide (TiO 2 ), cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), lead titanate (PbTiO 3 ), silicon titanate (SrTiO 3 ), lead zirconate (PbZrO 3 ), tungsten oxide (WO 3 ), yttrium oxide (Y 2 O 3 ), bismuth silicon oxide (Bi 4 Si 2 O 12 ), barium strontium titanate (BST) (Ba 1−x Sr x TiO 3 ), PMN (PbMg x Nb 1−x O 3 ), PZT (PbZr x Ti 1−x O 3 ), PZN (PbZn x Nb 1−x O 3 ), and PST (PbSc x Ta 1−x O 3 ).
Claim 3
Dependent Claim
19 words
The process of claim 1 , wherein the first interfacial barrier layer is deposited by ALCVD, RTCVD or MOCVD.
Claim 4
Dependent Claim
20 words
The process of claim 1 , wherein the layer of high-K dielectric material is deposited by ALCVD, RTCVD or MOCVD.
Claim 5
Dependent Claim
25 words
The process of claim 1 , further comprising depositing on the layer of high-K dielectric material a second interfacial barrier layer of a dielectric material.
Claim 6
Dependent Claim
26 words
The process of claim 4 , wherein the second interfacial barrier layer comprises a dielectric material comprising aluminum oxide, silicon oxynitride, silicon nitride or mixtures thereof.
Claim 7
Dependent Claim
20 words
The process of claim 4 , further comprising depositing a polysilicon or polysilicon-germanium layer over the second interfacial barrier layer.
Claim 8
Dependent Claim
177 words
A process for fabricating a semi conductor device having a high-K dielectric layer over a silicon substrate, comprising: depositing on the silicon substrate a first interfacial barrier layer of aluminum oxide; depositing on the first interfacial barrier layer a layer comprising at least one high-K dielectric material, wherein the high-K dielectric material comprises at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), barium titanate (BaTiO 3 ), titanium dioxide (TiO 2 ), cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), lead titanate (PbTiO 3 ), silicon titanate (SrTiO 3 ), lead zirconate (PbZrO 3 ), tungsten oxide (WO 3 ), yttrium oxide (Y 2 O 3 ), bismuth silicon oxide (Bi 4 Si 2 O 12 ), barium strontium titanate (BST) (Ba 1−x Sr x TiO 3 ), PMN (PbMg x Nb 1−x O 3 ), PZT (PbZr x Ti 1−x O 3 ), PZN (PbZn x Nb 1−x O 3 ), and PST (PbSc x Ta 1−x O 3 ).
Claim 9
Dependent Claim
177 words
A process for fabricating a semi conductor device having a high-K dielectric layer over a silicon substrate, comprising: depositing on the silicon substrate a first interfacial barrier layer of aluminum oxide; depositing on the first interfacial barrier layer a layer comprising at least one high-K dielectric material, wherein the high-K dielectric material comprises at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), barium titanate (BaTiO 3 ), titanium dioxide (TiO 2 ), cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), lead titanate (PbTiO 3 ), silicon titanate (SrTiO 3 ), lead zirconate (PbZrO 3 ), tungsten oxide (WO 3 ), yttrium oxide (Y 2 O 3 ), bismuth silicon oxide (Bi 4 Si 2 O 12 ), barium strontium titanate (BST) (Ba 1−x Sr x TiO 3 ), PMN (PbMg x Nb 1−x O 3 ), PZT (PbZr x Ti 1−x O 3 ), PZN (PbZn x Nb 1−x O 3 ), and PST (PbSc x Ta 1−x O 3 ).
Claim 10
Dependent Claim
19 words
The process of claim 7 , wherein the first interfacial barrier layer is deposited by ALCVD, RTCVD or MOCVD.
Claim 11
Dependent Claim
20 words
The process of claim 7 , wherein the layer of high-K dielectric material is deposited by ALCVD, RTCVD or MOCVD.
Claim 12
Dependent Claim
25 words
The process of claim 7 , further comprising depositing on the layer of high-K dielectric material a second interfacial barrier layer of a dielectric material.
Claim 13
Dependent Claim
26 words
The process of claim 10 , wherein the second interfacial barrier layer comprises a dielectric material comprising aluminum oxide, silicon oxynitride, silicon nitride or mixtures thereof.
Claim 14
Dependent Claim
21 words
The process of claim 10 , further comprising depositing a polysilicon or polysilicon germanium layer over the second interfacial barrier layer.
Claim 15
Dependent Claim
199 words
A process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, comprising: depositing on the silicon substrate a first interfacial barrier layer of silicon nitride, silicon oxynitride or mixtures thereof; depositing on the interfacial barrier layer a layer comprising at least one high-K dielectric material, with the proviso that the layer comprising at least one high-K dielectric material does not include a metal oxynitride, wherein the high-K dielectric material comprises at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), barium titanate (BaTiO 3 ), titanium dioxide (TiO 2 ), cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), lead titanate (PbTiO 3 ), silicon titanate (SrTiO 3 ), lead zirconate (PbZrO 3 ), tungsten oxide (WO 3 ), yttrium oxide (Y 2 O 3 ), bismuth silicon oxide (Bi 4 Si 2 O 12 ), barium strontium titanate (BST) (Ba 1−x Sr x TiO 3 ), PMN (PbMg x Nb 1−x O 3 ), PZT (PbZr x Ti 1−x O 3 ), PZN (PbZn x Nb 1−x O 3 ), and PST (PbSc x Ta 1−x O 3 ).
Claim 16
Dependent Claim
199 words
A process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, comprising: depositing on the silicon substrate a first interfacial barrier layer of silicon nitride, silicon oxynitride or mixtures thereof; depositing on the interfacial barrier layer a layer comprising at least one high-K dielectric material, with the proviso that the layer comprising at least one high-K dielectric material does not include a metal oxynitride, wherein the high-K dielectric material comprises at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), barium titanate (BaTiO 3 ), titanium dioxide (TiO 2 ), cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), lead titanate (PbTiO 3 ), silicon titanate (SrTiO 3 ), lead zirconate (PbZrO 3 ), tungsten oxide (WO 3 ), yttrium oxide (Y 2 O 3 ), bismuth silicon oxide (Bi 4 Si 2 O 12 ), barium strontium titanate (BST) (Ba 1−x Sr x TiO 3 ), PMN (PbMg x Nb 1−x O 3 ), PZT (PbZr x Ti 1−x O 3 ), PZN (PbZn x Nb 1−x O 3 ), and PST (PbSc x Ta 1−x O 3 ).
Claim 17
Dependent Claim
18 words
The process of claim 13 , wherein the interfacial barrier layer is deposited by ALCVD, RTCVD or MOCVD.
Claim 18
Dependent Claim
20 words
The process of claim 13 , wherein the layer of high-K dielectric material is deposited by ALCVD, RTCVD or MOCVD.
Claim 19
Dependent Claim
22 words
The process of claim 13 , further comprising depositing a second interfacial barrier layer on the layer comprising a high-K dielectric material.
Claim 20
Dependent Claim
21 words
The process of claim 16 , further comprising depositing a polysilicon or polysilicon germanium layer over the second interfacial barrier layer.
Claim 21
Dependent Claim
38 words
The process of claim 1 , wherein the interfaial barrier layer is deposited to a thickness in the range from about 1 to about 5 monolayers of molecules of material of which the interfacial barrier layer is comprised.
Claim 22
Dependent Claim
40 words
The process of claim 4 , wherein the second interfacial barrier layer is deposited to a thickness in the range from about 1 to about 5 monolayers of molecules of material of which the second interfacial barrier layer is comprised.
Claim 23
Dependent Claim
29 words
The process of claim 7 , wherein the interfacial barrier layer is deposited to a thickness in the range from about 1 to about 5 monolayers of aluminum oxide.
Claim 24
Dependent Claim
38 words
The process of claim 13 , wherein the interfacial barrier layer is deposited to a thickness in the range from about 1 to about 5 monolayers of molecules of material of which die interfacial barrier layer is comprised.
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