System of management of the trimming of integrated fuses within a scan test architecture

Claim 2

A multifunction circuit for controlling, simulating and burning integrated fuses according to a post fabrication trimming procedure and for performing scan tests of at least one circuit to be trimmed in an integrated device, the multifunction circuit comprising: a scan chain comprising a plurality of scan flip-flops connected together in series; and a trimming circuit connected to said scan chain, to the at least one circuit to be trimmed and to the integrated fuses, said trimming circuit comprising a fuse register comprising a first array of N scan flip-flops including N outputs connected to N inputs of the at least one circuit to be trimmed, with N being equal to a number of integrated fuses, and a first scan flip-flop of said first array includes a scan command input for receiving a scan command, a counter register comprising a second array of K scan flip-flops, a first scan flip-flop of said second array includes a scan command input connected to the output of a last scan flip-flop of said first array, and a control register comprising a third array of M scan flip-flops being configured as memory cells for storing trimming parameters, and a first scan flip-flop of said third array includes a scan command input connected to an output of a last flip-flop of said second array and an output of a last scan flip-flop of said third array is connected to a scan command input of a first scan flip-flop of said scan chain.

Claim 3

A multifunction circuit according to claim 1 , wherein said counter register further comprises a modulus N counter connected to said second array.

Claim 4

A multifunction circuit according to claim 1 , wherein each scan flip-flop of said scan chain, and said first, second and third arrays includes an input for receiving in common a timing signal.

Claim 5

A multifunction circuit according to claim 1 , further comprising a decoder connected to outputs of said third array.

Claim 6

A multifunction circuit according to claim 4 , further comprising a logic circuit connected to outputs of said decoder circuit, to outputs of said first array, said logic circuit also including inputs for receiving an enabling signal and a condition signal for conditioning a sequential burning of selected integrated fuses, the condition signal being applied through a fifth external pin of the integrated device.

Claim 7

A multifunction circuit according to claim 5 , wherein said fuse register further comprises: N input logic gates, each input logic gate being connected to a command input of a respective scan flip-flop of said first array; and a bus connected to an output of said logic circuit for providing an N number of generated burning commands to respective inputs of said N input logic gates for controlling the command inputs thereof.

Claim 8

A multifunction circuit according to claim 1 , further comprising a first circuit to be subjected to functionality tests and being connected to said scan chain, wherein each scan flip-flop in said scan chain includes a command input connected to a respective output of said first circuit.

Claim 9

A multifunction circuit according to claim 1 , further comprising a second circuit to be subjected to functionality tests and being connected to said scan chain, wherein each scan flip-flop in said scan chain includes an output connected to a respective input of said second circuit.

Claim 10

A multifunction circuit according to claim 1 , wherein a first through a next to last scan flip-flop of said plurality of scan flip-flops in said scan chain each includes an output connected to a second scan input of a successive scan flip-flop.

Claim 11

A multifunction circuit according to claim 9 , wherein said first scan flip-flop includes a second scan input for receiving at least a scan bit vector connected through a first external pin of the integrated device.

Claim 12

A multifunction circuit according to claim 9 , wherein an output of a last scan flip-flop of said plurality of scan flip-flops in said scan chain is connected to a second external pin of the integrated device.

Claim 13

A multifunction circuit according to claim 1 , wherein each scan flip-flop in said scan chain includes a conditioning input for receiving an enabling signal of a scan being applied through a third external pin of the integrated circuit.

Claim 14

A multifunction circuit according to claim 1 , wherein each scan flip-flop in said scan chain includes a timing input for receiving a scan timing signal being applied through a fourth external pin of the integrated circuit.

Claim 15

A multifunction circuit according to claim 1 , wherein said trimming circuit is placed upstream of said scan chain.

Claim 16

A multifunction circuit according to claim 1 , wherein said trimming circuit is placed downstream of said scan chain.

Claim 17

A multifunction circuit according to claim 1 , wherein said plurality of scan flip-flops of said scan chain are divided into first and second blocks of scan flip-flops, and wherein said trimming circuit is connected between said first and second blocks.

Claim 18

An integrated circuit comprising: a plurality of external pins; a plurality of integrated fuses; at least one circuit to be trimmed; a multifunction circuit for controlling, simulating and burning said integrated fuses according to a post fabrication trimming procedure and for performing scan tests of said at least one circuit to be trimmed, said multifunction circuit comprising: a scan chain comprising a plurality of scan flip-flops connected together in series, and a trimming circuit connected to said scan chain, to said at least one circuit to be trimmed and to said plurality of integrated fuses, said trimming circuit comprising a fuse register comprising a first array of N scan flip-flops including N outputs connected to N inputs of said at least one circuit to be trimmed, with N being equal to a number of said plurality of integrated fuses, and a first scan flip-flop of said first array includes a scan command input for receiving a scan command, a counter register comprising a second array of K scan flip-flops, a first scan flip-flop of said second array includes a scan command input connected to the output of a last scan flip-flop of said first array, and a control register comprising a third array of M scan flip-flops being configured as memory cells for storing trimming parameters, and a first scan flip-flop of said third array includes a scan command input connected to an output of a last flip-flop of said second array and an output of a last scan flip-flop of said third array is connected to a scan command input of a first scan flip-flop of said scan chain.

Claim 19

An integrated circuit comprising: a plurality of external pins; a plurality of integrated fuses; at least one circuit to be trimmed; a multifunction circuit for controlling, simulating and burning said integrated fuses according to a post fabrication trimming procedure and for performing scan tests of said at least one circuit to be trimmed, said multifunction circuit comprising: a scan chain comprising a plurality of scan flip-flops connected together in series, and a trimming circuit connected to said scan chain, to said at least one circuit to be trimmed and to said plurality of integrated fuses, said trimming circuit comprising a fuse register comprising a first array of N scan flip-flops including N outputs connected to N inputs of said at least one circuit to be trimmed, with N being equal to a number of said plurality of integrated fuses, and a first scan flip-flop of said first array includes a scan command input for receiving a scan command, a counter register comprising a second array of K scan flip-flops, a first scan flip-flop of said second array includes a scan command input connected to the output of a last scan flip-flop of said first array, and a control register comprising a third array of M scan flip-flops being configured as memory cells for storing trimming parameters, and a first scan flip-flop of said third array includes a scan command input connected to an output of a last flip-flop of said second array and an output of a last scan flip-flop of said third array is connected to a scan command input of a first scan flip-flop of said scan chain.

Claim 20

An integrated circuit according to claim 17 , wherein said counter register further comprises a modulus N counter connected to said second array.

Claim 21

An integrated circuit according to claim 17 , wherein each scan flip-flop of said scan chain, and said first, second and third arrays includes an input for receiving in common a timing signal.

Claim 22

An integrated circuit according to claim 17 , further comprising a decoder connected to outputs of said third array.

Claim 23

An integrated circuit according to claim 20 , further comprising a logic circuit connected to outputs of said decoder circuit, to outputs of said first array, said logic circuit also including inputs for receiving an enabling signal and a condition signal for conditioning a sequential burning of selected integrated fuses, the condition signal being applied through a fifth external pin of said plurality of external pins.

Claim 24

An integrated circuit according to claim 21 , wherein said fuse register further comprises: N input logic gates, each input logic gate being connected to a command input of a respective scan flip-flop of said first array; and a bus connected to an output of said logic circuit for providing an N number of generated burning commands to respective inputs of said N input logic gates for controlling the command inputs thereof.

Claim 25

An integrated circuit according to claim 17 , further comprising a first circuit to be subjected to functionality tests and being connected to said scan chain, wherein each scan flip-flop in said scan chain includes a command input connected to a respective output of said first circuit.

Claim 26

An integrated circuit according to claim 17 , further comprising a second circuit to be subjected to functionality tests and being connected to said scan chain, wherein each scan flip-flop in said scan chain includes an output connected to a respective input of said second circuit.

Claim 27

An integrated circuit according to claim 17 , wherein a first through a next to last scan flip-flop of said plurality of scan flip-flops in said scan chain each includes an output connected to a second scan input of a successive scan flip-flop.

Claim 28

An integrated circuit according to claim 17 , wherein said first scan flip-flop includes a second scan input for receiving at least a scan bit vector connected through a first external pin of said plurality of external pins.

Claim 29

An integrated circuit according to claim 17 , wherein an output of a last scan flip-flop of said plurality of scan flip-flops in said scan chain is connected to a second external pin of said plurality of external pins.

Claim 30

An integrated circuit according to claim 17 , wherein each scan flip-flop in said scan chain includes a conditioning input for receiving an enabling signal of a scan being applied through a third external pin of said plurality of external pins.

Claim 31

An integrated circuit according to claim 17 , wherein each scan flip-flop in said scan chain includes a timing input for receiving a scan timing signal being applied through a fourth external pin of said plurality of external pins.

Claim 32

An integrated circuit according to claim 17 , wherein said trimming circuit is placed upstream of said scan chain.

Claim 33

An integrated circuit according to claim 17 , wherein said trimming circuit is placed downstream of said scan chain.

Claim 34

An integrated circuit according to claim 17 , wherein said plurality of scan flip-flops of said scan chain are divided into first and second blocks of scan flip-flops, and wherein said trimming circuit is connected between said first and second blocks.

Claim 37

A method according to claim 33 , further comprising connecting a modulus N counter to the second array.

Claim 38

A method according to claim 33 , wherein each scan flip-flop of the scan chain, and the first, second and third arrays includes an input for receiving in common a timing signal.

Claim 39

A method according to claim 33 , further comprising connecting a decoder to outputs of the third array.

Claim 40

A method according to claim 36 , further comprising connecting a logic circuit to outputs of the decoder circuit, to outputs of the first array, the logic circuit also including inputs for receiving an enabling signal and a condition signal for conditioning a sequential burning of selected integrated fuses, the condition signal being applied through a fifth external pin of the integrated circuit.

Claim 41

A method according to claim 37 , further comprising: connecting a respective input logic gate to each command input of each scan flip-flop of the first array; and connecting a bus to an output of the logic circuit for providing an N number of generated burning commands to respective inputs of the input logic gates for controlling the command inputs thereof.

Claim 42

A method according to claim 33 , further comprising connecting a first circuit to be subjected to functionality tests to the scan chain, wherein each scan flip-flop in the scan chain includes a command input connected to a respective output of the first circuit.

Claim 43

A method according to claim 33 , further comprising connecting a second circuit to be subjected to functionality tests to the scan chain, wherein each scan flip-flop in the scan chain includes an output connected to a respective input of the second circuit.

Claim 44

A method according to claim 33 , further comprising connecting an output of a first through a next to last scan flip-flop of the plurality of scan flip-flops in the scan chain to a second scan input of a successive scan flip-flop.

Claim 45

A method according to claim 41 , further comprising connecting a second scan input of the first scan flip-flop to a first external pin of the integrated circuit for receiving at least a scan bit vector.

Claim 46

A method circuit according to claim 41 , further comprising connecting an output of a last scan flip-flop of the plurality of scan flip-flops in the scan chain to a second external pin of the integrated circuit.

Claim 47

A method according to claim 33 , wherein each scan flip-flop in the scan chain includes a conditioning input for receiving an enabling signal of a scan being applied through a third external pin of the integrated circuit.

Claim 48

A method according to claim 33 , wherein each scan flip-flop in the scan chain includes a timing input for receiving a scan timing signal being applied through a fourth external pin of the integrated circuit.

Claim 49

A method according to claim 33 , wherein the trimming circuit is placed upstream of the scan chain.

Claim 50

A method according to claim 33 , wherein the trimming circuit is placed downstream of the scan chain.

Claim 51

A method according to claim 33 , wherein the plurality of scan flip-flops of the scan chain are divided into first and second blocks of scan flip-flops, and wherein the trimming circuit is connected between the first and second blocks.