US6675359B2
Expired / Lapsed
US
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Recognition of a state machine in high-level integrated circuit description language code
Assignee: Mentor Graphics Corp
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Filing: 1998-08-26
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Granted: 2004-01-06
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Expires: 2018-08-26
Abstract
Abstract A method and apparatus for recognizing a state machine in circuit design in a high-level IC description language. The present invention analyzes high-level IC description language code, such as VHDL and Verilog®, of an IC design and extracts description information corresponding to a state machine. The description information can be, for example, the high-level IC description language code corresponding to the state machine, a state diagram of the state machine, a state table for the state machine, or other representation of the state machine. In one embodiment, the present invention identifies a set of one or more processes as defined by VHDL “process” statements. By identifying one or more clocked processes, one or more transition processes, and one or more output processes, the present invention provides a state machine summary to describe the state machine identified in the high-level IC description language code.
Inventors
- 👤 Michael E.J. Gilford
- 👤 Gordon N. Walker
- 👤 Jacob L. Tredinnick
- 👤 Mark W.P. Dane
- 👤 Michael J. Reynolds
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:07
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
114 words
A method for identifying an integrated circuit (IC) implementation of a state machine in a high-level IC description language code comprising: identifying one or more transition processes within the high-level IC description language code; identifying one or more clocked processes within the high-level IC description language code; identifying one or more output processes within the high-level IC description language code; and building a state machine summary based at least in part on the one or more identified transition processes, wherein building the state machine summary is based at least in part on the one or more identified transition processes, the one or more identified clocked processes and the one or more identified output processes.
Claim 2
Independent Claim
114 words
A method for identifying an integrated circuit (IC) implementation of a state machine in a high-level IC description language code comprising: identifying one or more transition processes within the high-level IC description language code; identifying one or more clocked processes within the high-level IC description language code; identifying one or more output processes within the high-level IC description language code; and building a state machine summary based at least in part on the one or more identified transition processes, wherein building the state machine summary is based at least in part on the one or more identified transition processes, the one or more identified clocked processes and the one or more identified output processes.
Claim 3
Dependent Claim
68 words
The method of claim 1 wherein identifying one or more clocked processes further comprises: determining whether the one or more clocked processes includes a sensitivity list; identifying a first IF statement in the one or more clocked processes for each clocked process that includes a sensitivity list; identifying conditions associated with the IF statement, if any; and determining a clock clause from the IF statement and associated conditions.
Claim 4
Dependent Claim
43 words
The method of claim 2 wherein the determining the clock clause further comprises: checking a form of the clock clause; checking for an assignment to a state variable by the clock clause; and checking for a case statement test of the state variable.
Claim 5
Dependent Claim
18 words
The method of claim 2 further comprising determining a reset clause from the IF statement as associated conditions.
Claim 6
Dependent Claim
24 words
The method of claim 2 farther comprising: identifying a current state variable for the process; and identifying a next state variable for the process.
Claim 7
Dependent Claim
26 words
The method of claim 1 wherein determining the one or more transition processes comprises identifying a process that assigns a value to a next state variable.
Claim 8
Dependent Claim
20 words
The method of claim 1 wherein building a state machine summary comprises generating a graphical representation of the state machine.
Claim 9
Dependent Claim
20 words
The method of claim 1 wherein building a state machine summary comprises generating a textual description of the state machine.
Claim 10
Dependent Claim
112 words
A machine-readable medium having stored thereon sequences of instructions, which when executed by a processor cause the processor to: identify one or more transition processes within a high-level IC description language code; identify one or more clocked processes within the high-level IC description language code; identify one or more output processes within the high-level IC description language code; and build a state machine summary based at least in part on the one or more identified transition processes, wherein building the state machine summary is based at least in part on the one or more identified transition processes, the one or more identified clocked processes and the one or more identified output processes.
Claim 11
Dependent Claim
112 words
A machine-readable medium having stored thereon sequences of instructions, which when executed by a processor cause the processor to: identify one or more transition processes within a high-level IC description language code; identify one or more clocked processes within the high-level IC description language code; identify one or more output processes within the high-level IC description language code; and build a state machine summary based at least in part on the one or more identified transition processes, wherein building the state machine summary is based at least in part on the one or more identified transition processes, the one or more identified clocked processes and the one or more identified output processes.
Claim 12
Dependent Claim
86 words
The machine-readable medium of claim 9 wherein the sequences of instructions that cause the processor to identify one or more clocked processes further comprise sequences of instructions that cause the processor to: determine whether the one or more clocked processes includes a sensitivity list; identify a first IF statement in the one or more clocked processes for each clocked process that includes a sensitivity list; identify conditions associated with the IF statement, if any; and determine a clock clause from the IF statement and associated conditions.
Claim 13
Dependent Claim
62 words
The machine-readable medium of claim 10 wherein the sequences of instructions to cause the processor to determine the clock clause further comprise sequences of instructions, which when executed cause the processor to: check a form of the clock clause; check for an assignment to a state variable by the clock clause; and check for a case statement test of the state variable.
Claim 14
Dependent Claim
29 words
The machine-readable medium of claim 10 further comprising sequences of instructions, which when executed cause the processor to determine a reset clause from the IF statement as associated conditions.
Claim 15
Dependent Claim
35 words
The machine-readable medium of claim 10 further comprising sequences of instructions, which when executed cause the processor to: identify a current state variable for the process; and identify a next state variable for the process.
Claim 16
Dependent Claim
45 words
The machine-readable medium of claim 9 wherein the sequences of instructions that cause the processor to determine the one or more transition processes further comprise sequences of instructions that cause the processor to identify a process that assigns a value to a next state variable.
Claim 17
Dependent Claim
38 words
The machine-readable medium of claim 9 wherein the sequences of instructions that cause the processor to build a state machine summary comprise sequences of instructions that cause the processor to generate a graphical representation of the state machine.
Claim 18
Dependent Claim
38 words
The machine-readable medium of claim 9 wherein the sequences of instructions that cause the processor to build a state machine summary comprise sequences of instructions that cause the processor to generate a textual description of the state machine.
Claim 19
Independent Claim
120 words
An apparatus that identifies an integrated circuit (IC) implementation of a state machine in a high-level IC description language code comprising: identifying one or more transition processes within the high-level IC description language code; means for identifying one or more clocked processes within the high-level IC description language code; means for identifying one or more output processes within the high-level IC description language code; and means for building a state machine summary based at least in part on the one or more identified transition processes, wherein building the state machine summary is based at least in part on the one or more identified transition processes, the one or more identified clocked processes and the one or more identified output processes.
Claim 20
Independent Claim
120 words
An apparatus that identifies an integrated circuit (IC) implementation of a state machine in a high-level IC description language code comprising: identifying one or more transition processes within the high-level IC description language code; means for identifying one or more clocked processes within the high-level IC description language code; means for identifying one or more output processes within the high-level IC description language code; and means for building a state machine summary based at least in part on the one or more identified transition processes, wherein building the state machine summary is based at least in part on the one or more identified transition processes, the one or more identified clocked processes and the one or more identified output processes.
Claim 21
Dependent Claim
79 words
The apparatus of claim 17 wherein the means for identifying one or more clocked processes further comprises: means for determining whether the one or more clocked processes includes a sensitivity list; means for identifying a first IF statement in the one or more clocked processes for each clocked process that includes a sensitivity list; means for identifying conditions associated with the IF statement, if any; and means for determining a clock clause from the IF statement and associated conditions.
Claim 22
Dependent Claim
51 words
The apparatus of claim 18 wherein the means for determining the clock clause further comprises: means for checking a form of the clock clause; means for checking for an assignment to a state variable by the clock clause; and means for checking for a case statement test of the state variable.
Claim 23
Dependent Claim
20 words
The apparatus of claim 18 further comprising means for determining a reset clause from the IF statement as associated conditions.
Claim 24
Dependent Claim
28 words
The apparatus of claim 18 further comprising: means for identifying a current state variable for the process; and means for identifying a next state variable for the process.
Claim 25
Dependent Claim
31 words
The apparatus of claim 17 wherein the means for determining the one or more transition process comprises means for identifying a process that assigns a value to a next state variable.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2007-01-05 | 2007-07-07 | 2008-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-01-05 | 2011-07-07 | 2012-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-01-05 | 2015-07-07 | 2016-01-06 | $7700.00 | Window Closed / Lapsed |