Abstract The method implements implicit sequential behavior using a general finite state machine architecture (FSM) through the systematic evaluation of control flow graphs (CFGs) having one or more weight statements which are sensitive to the same unique clock edge. Each of the weight statements contained in the CFG are assigned a state in the state machine. All of the executable paths between each weight statement are fully evaluated on a node-by-node basis. From this evaluation process, expressions are extracted which define combinational logic necessary to produce additional inputs to the FSM to produce the next state, as well as expressions representing outputs of the FSM as associated with each transition from one state to another. The method also deals with proper evaluation of unrollable loops.
Inventors
👤 Jean-Charles Giomi
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-01 08:10
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
156 words
A method of extracting finite state machine (FSM) circuit architecture in the form of a structural netlist from implicit sequential behavior specified in a hardware description language (-HDL) circuit description, said method comprising the steps of: Parsing the HDL description to create a plurality of control flow graphs (CFGs) by performing lexical and syntactic analysis for each process of the HDL description; Identifying one or more of said plurality of CFGs which specify implicit sequential behavior incorporating one or more wait nodes each of which are sensitive to the same unique clock edge; Evaluating each of the nodes of the identified CFGs using a breadth first search, said step of evaluating further comprising the steps of: Assigning each of the wait nodes to a state; Evaluating all executable paths between each of the wait nodes; Building a state transition table (STT) based on said step of evaluating; and Generating a structural netlist based on the STTs.
Claim 2
Independent Claim
156 words
A method of extracting finite state machine (FSM) circuit architecture in the form of a structural netlist from implicit sequential behavior specified in a hardware description language (-HDL) circuit description, said method comprising the steps of: Parsing the HDL description to create a plurality of control flow graphs (CFGs) by performing lexical and syntactic analysis for each process of the HDL description; Identifying one or more of said plurality of CFGs which specify implicit sequential behavior incorporating one or more wait nodes each of which are sensitive to the same unique clock edge; Evaluating each of the nodes of the identified CFGs using a breadth first search, said step of evaluating further comprising the steps of: Assigning each of the wait nodes to a state; Evaluating all executable paths between each of the wait nodes; Building a state transition table (STT) based on said step of evaluating; and Generating a structural netlist based on the STTs.