US6668364B2
Expired / Lapsed
US
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Methods and apparatuses for designing integrated circuits
Assignee: Synopsys Inc
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Filing: 2002-06-03
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Granted: 2003-12-23
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Expires: 2022-06-03
Abstract
Abstract Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTh netlist is mapped to a particular target technology (e.g. a particular IC vendor's architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e.g. field programmable gate arrays). Other examples of methods and apparatuses are described.
Inventors
- 👤 Kenneth S. McElvain
- 👤 Robert Erickson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 17:49
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/323; G06F30/327; G06F30/39; G06F30/392
Claims Analysis
Total Claims: 52
Claim 1
Independent Claim
39 words
A system of designing a plurality of integrated circuits (ICs), said system comprising: means for displaying a representation of said plurality of ICs; means for partitioning a technology independent RTL (register transfer level) netlist between said plurality of ICs.
Claim 2
Independent Claim
39 words
A system of designing a plurality of integrated circuits (ICs), said system comprising: means for displaying a representation of said plurality of ICs; means for partitioning a technology independent RTL (register transfer level) netlist between said plurality of ICs.
Claim 3
Dependent Claim
30 words
A system as in claim 1 further comprising: means for compiling a hardware description language (HDL) code, wherein said technology independent RTL netlist is produced after compiling said HDL code.
Claim 4
Dependent Claim
15 words
A system as in claim 2 wherein said ICs each comprise a programmable logic device.
Claim 5
Dependent Claim
21 words
A system as in claim 2 further comprising: means for mapping said technology independent RTh netlist to a selected technology architecture.
Claim 6
Dependent Claim
14 words
A system as in claim 4 wherein said mapping is performed after said partitioning.
Claim 7
Dependent Claim
28 words
A system as in claim 4 further comprising: means for performing a place and route operation after said mapping to implement said ICs in said selected technology architecture.
Claim 8
Dependent Claim
21 words
A system as in claim 4 further comprising: means for optimizing a design of each of said ICs after said partitioning.
Claim 9
Dependent Claim
20 words
A system as in claim 7 wherein said optimizing optimizes each of said ICs by removing duplicative logic or input/outputs.
Claim 10
Dependent Claim
17 words
A system as in claim 4 wherein said HDL code is created without regard to said partitioning.
Claim 11
Dependent Claim
17 words
A system as in claim 7 wherein said optimizing and said mapping are performed after said partitioning.
Claim 12
Dependent Claim
48 words
A system as in claim 4 further comprising: means for mapping portions of said technology independent RTL netlist to a selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 13
Dependent Claim
23 words
A system as in claim 4 further comprising: means for optimizing interconnects between modules of said technology independent RTL netlist before said partitioning.
Claim 14
Dependent Claim
18 words
A system as in claim 11 wherein said estimates are used to decide how to perform said partitioning.
Claim 15
Dependent Claim
23 words
A system as in claim 13 wherein a user considers said estimates and selects a command to decide how to perform said partitioning.
Claim 16
Dependent Claim
51 words
A system as in claim 4 wherein said ICs each comprise a programmable logic device and wherein said system further comprises: means for testing a prototype of a system with said ICs; means for performing a synthesis of said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).
Claim 17
Dependent Claim
63 words
A digital processing system for use in designing a plurality of integrated circuits (ICs), said digital processing system comprising: a display device; a memory; a processor coupled to said memory and to said display device, said processor partitioning a technology independent RTL (register transfer level) netlist between representations of said plurality of ICs, said technology independent RTL netlist being stored in said memory.
Claim 18
Dependent Claim
63 words
A digital processing system for use in designing a plurality of integrated circuits (ICs), said digital processing system comprising: a display device; a memory; a processor coupled to said memory and to said display device, said processor partitioning a technology independent RTL (register transfer level) netlist between representations of said plurality of ICs, said technology independent RTL netlist being stored in said memory.
Claim 19
Dependent Claim
25 words
A digital processing system as in claim 16 wherein said processor compiles a hardware description language (HDL) code to produce said technology independent RTL netlist.
Claim 20
Dependent Claim
17 words
A digital processing system as in claim 17 wherein said ICs each comprise a programmable logic device.
Claim 21
Dependent Claim
22 words
A digital processing system as in claim 17 wherein said processor maps said technology independent RTh netlist to a selected technology architecture.
Claim 22
Dependent Claim
26 words
A digital processing system as in claim 19 wherein said processor maps said technology independent RTh netlist after said processor partitions said technology independent RTL netlist.
Claim 23
Dependent Claim
42 words
A digital processing system as in claim 19 wherein said processor performs a place and route operation after said processor maps said technology independent RTh netlist, wherein said place and route operation creates a representation of circuitry in said selected technology architecture.
Claim 24
Dependent Claim
28 words
A digital processing system as in claim 20 wherein said processor optimizes a design of each of said ICs after said processor partitions said technology independent RTL netlist.
Claim 25
Dependent Claim
26 words
A digital processing system as in claim 21 wherein said processor maps said technology independent RTh netlist after said processor partitions said technology independent RTL netlist.
Claim 26
Dependent Claim
44 words
A digital processing system as in claim 23 wherein said processor maps portions of said technology independent RTL netlist to said selected technology architecture to generate estimates of IC resources and wherein said processor maps said portions after said processor compiles said HDL code.
Claim 27
Dependent Claim
25 words
A digital processing system as in claim 23 wherein said processor displays said estimates on said display device and stores said estimates in said memory.
Claim 28
Dependent Claim
53 words
A digital processing system as in claim 25 wherein said processor displays graphical representations of said plurality of ICs on said display device and displays on said display device representations of portions of said technology independent RTL netlist and wherein said processor performs said partitioning in response to a command from a user.
Claim 29
Independent Claim
62 words
A system for designing a plurality of integrated circuits (ICs), said system comprising: means for compiling a hardware description language (HDL) code to produce an RTL netlist representation which specifies said plurality of ICs; means for selecting logic designed for placement on one of said plurality of ICs and replicating said logic for placement on another one of said plurality of ICs.
Claim 30
Independent Claim
62 words
A system for designing a plurality of integrated circuits (ICs), said system comprising: means for compiling a hardware description language (HDL) code to produce an RTL netlist representation which specifies said plurality of ICs; means for selecting logic designed for placement on one of said plurality of ICs and replicating said logic for placement on another one of said plurality of ICs.
Claim 31
Dependent Claim
21 words
A system as in claim 27 further comprising: means for partitioning said RTL netlist representation to specify said plurality of ICs.
Claim 32
Dependent Claim
28 words
A system as in claim 28 further comprising: means for mapping said RTL netlist representation to a selected technology architecture, wherein said RTL netlist representation is technology independent.
Claim 33
Dependent Claim
18 words
A system as in claim 29 wherein each of said plurality of ICs comprises a programmable logic device.
Claim 34
Dependent Claim
14 words
A system as in claim 29 wherein said mapping is performed after said partitioning.
Claim 35
Dependent Claim
27 words
A system as in claim 31 further comprising: means for performing a place and route operation after said mapping to implement logic in said plurality of ICs.
Claim 36
Dependent Claim
23 words
A system as in claim 32 further comprising: means for optimizing a design of each of said plurality of ICs after said partitioning.
Claim 37
Dependent Claim
18 words
A system as in claim 27 wherein said HDL code is created without specifying a plurality of ICs.
Claim 38
Dependent Claim
47 words
A system as in claim 29 further comprising: means for mapping portions of said RTL netlist representation to said selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 39
Dependent Claim
20 words
A system as in claim 35 wherein said estimates are used to decide how to perform said selecting and replicating.
Claim 40
Dependent Claim
43 words
A system as in claim 30 further comprising: means for testing a prototype of a system with said plurality of ICs; means for performing, after said testing, a synthesis on said HI)L code to generate at least one Application Specific Integrated Circuit (ASIC).
Claim 41
Independent Claim
69 words
A system for designing a plurality of integrated circuits (ICs), said system comprising: means for compiling a hardware description language (HDL) code to produce an RTL netlist representation; means for selecting one RTL component in said RTL netlist representation and splitting said one RTL component into a first RTL component designed for placement on a first IC and a second RTL component designed for placement on a second IC.
Claim 42
Independent Claim
69 words
A system for designing a plurality of integrated circuits (ICs), said system comprising: means for compiling a hardware description language (HDL) code to produce an RTL netlist representation; means for selecting one RTL component in said RTL netlist representation and splitting said one RTL component into a first RTL component designed for placement on a first IC and a second RTL component designed for placement on a second IC.
Claim 43
Dependent Claim
24 words
A system as in claim 38 further comprising: means for partitioning said RTL netlist representation to specify said first IC and said second IC.
Claim 44
Dependent Claim
28 words
A system as in claim 39 further comprising: means for mapping said RTL netlist representation to a selected technology architecture, wherein said RTL netlist representation is technology independent.
Claim 45
Dependent Claim
21 words
A system as in claim 40 wherein each of said first IC and said second IC comprises a programmable logic device.
Claim 46
Dependent Claim
14 words
A system as in claim 40 wherein said mapping is performed after said partitioning.
Claim 47
Dependent Claim
48 words
A system as in claim 42 further comprising: means for performing a place and route operation after said mapping to implement logic for said first RTL component for placement on said first IC and to implement logic for said second RTL component for placement on said second IC.
Claim 48
Dependent Claim
20 words
A system as in claim 40 wherein said one RTL component is created as a unitary object after said compiling.
Claim 49
Dependent Claim
30 words
A system as in claim 40 wherein said one RTL component is a large RTL component having more inputs/outputs than is available on said first IC or said second IC.
Claim 50
Dependent Claim
47 words
A system as in claim 40 further comprising: means for mapping portions of said RTL netlist representation to said selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 51
Dependent Claim
21 words
A system as in claim 46 wherein said selecting and said splitting are performed after said compiling and before said mapping.
Claim 52
Dependent Claim
20 words
A system as in claim 47 wherein said estimates are used to determine how to split said one RTL component.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-12-22 | 2007-06-23 | 2007-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-12-22 | 2011-06-23 | 2011-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-12-22 | 2015-06-23 | 2015-12-23 | $7700.00 | Window Closed / Lapsed |