US6519754B1
Expired / Lapsed
US
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Methods and apparatuses for designing integrated circuits
Assignee: Synopsys Inc
•
Filing: 1999-05-17
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Granted: 2003-02-11
•
Expires: 2019-05-17
Abstract
Abstract Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.
Inventors
- 👤 Kenneth S. McElvain
- 👤 Robert Erickson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:28
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/323; G06F30/327
Claims Analysis
Total Claims: 77
Claim 1
Independent Claim
47 words
A method for designing an integrated circuit (IC), said method comprising: compiling a hardware description language (HDL) code to produce a technology independent RTL (register transfer level) netlist; allocating a portion of an area of said IC to a specific portion of said technology independent RTL netlist.
Claim 2
Independent Claim
47 words
A method for designing an integrated circuit (IC), said method comprising: compiling a hardware description language (HDL) code to produce a technology independent RTL (register transfer level) netlist; allocating a portion of an area of said IC to a specific portion of said technology independent RTL netlist.
Claim 3
Dependent Claim
22 words
A method as in claim 1 wherein said allocating restricts circuitry created from said specific portion to said portion of said IC.
Claim 4
Dependent Claim
19 words
A method as in claim 1 further comprising: mapping said technology independent RTL netlist to a selected technology architecture.
Claim 5
Dependent Claim
22 words
A method as in claim 3 wherein said IC comprises one of a programmable logic device or an Application Specific IC (ASIC).
Claim 6
Dependent Claim
14 words
A method as in claim 3 wherein said mapping is performed after said allocating.
Claim 7
Dependent Claim
26 words
A method as in claim 3 further comprising: performing a place and route operation after said mapping to implement said IC in said selected technology architecture.
Claim 8
Dependent Claim
17 words
A method as in claim 3 further comprising: optimizing a design of said IC after said allocating.
Claim 9
Dependent Claim
18 words
A method as in claim 7 wherein said optimizing optimizes said IC by removing duplicative logic or input/outputs.
Claim 10
Dependent Claim
17 words
A method as in claim 7 wherein said optimizing and said mapping are performed after said allocating.
Claim 11
Dependent Claim
17 words
A method as in claim 3 wherein said HDL code is created without regard to said allocating.
Claim 12
Dependent Claim
46 words
A method as in claim 3 further comprising: mapping portions of said technology independent RTL netlist to a selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 13
Dependent Claim
18 words
A method as in claim 11 wherein said estimates are used to decide how to perform said allocating.
Claim 14
Dependent Claim
21 words
A method as in claim 3 further comprising: optimizing interconnects between modules of said technology independent RTL netlist before said allocating.
Claim 15
Dependent Claim
23 words
A method as in claim 12 wherein a user considers said estimates and selects a command to decide how to perform said allocating.
Claim 16
Dependent Claim
46 words
A method as in claim 3 wherein said IC comprises a programmable logic device and wherein said method further comprises: testing a prototype of a system with said IC; performing a synthesis of said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).
Claim 17
Dependent Claim
22 words
A method as in claim 3 further comprising: partitioning said technology independent RTL netlist between representations of said IC and another IC.
Claim 18
Dependent Claim
14 words
A method as in claim 16 wherein said partitioning is performed before said mapping.
Claim 19
Dependent Claim
38 words
A method as in claim 16 further comprising: selecting logic designed for placement on one of said IC and said another IC and replicating said logic for placement on the other of said IC and said another IC.
Claim 20
Dependent Claim
47 words
A method as in claim 16 further comprising: selecting one RTL component in said technology independent RTL netlist and splitting said one RTL component into a first RTL component designed for placement on said IC and a second RTL component designed for placement on said another IC.
Claim 21
Dependent Claim
43 words
A method as in claim 1 further comprising: selecting logic designed for placement in one of said area of said IC and another area of said IC and replicating said logic for placement on the other of said area and said another area.
Claim 22
Dependent Claim
52 words
A method as in claim 1 further comprising: selecting one RTL component in said technology independent RTL netlist and splitting said one RTL component into a first RTL component designed for placement in said area of said IC and a second RTL component designed for placement in another area of said IC.
Claim 23
Dependent Claim
56 words
A machine readable medium as in claim 21 , said method further comprising: selecting one RTL component in said technology independent RTL netlist and splitting said one RTL component into a first.RTL component designed for placement in said area of said IC and a second RTL component designed for placement in another area of said IC.
Claim 24
Dependent Claim
64 words
A digital processing system for use in designing an integrated circuit (IC), said digital processing system comprising: a display device; a memory; a processor coupled to said memory and to said display device, said processor allocating a specific portion of a technology independent RTL (register transfer level) netlist to a portion of said IC, said technology independent RTL netlist being stored in said memory.
Claim 25
Dependent Claim
64 words
A digital processing system for use in designing an integrated circuit (IC), said digital processing system comprising: a display device; a memory; a processor coupled to said memory and to said display device, said processor allocating a specific portion of a technology independent RTL (register transfer level) netlist to a portion of said IC, said technology independent RTL netlist being stored in said memory.
Claim 26
Dependent Claim
42 words
A digital processing system as in claim 23 wherein said processor compiles a hardware description language (HDL) code to produce said technology independent RTL netlist and wherein said allocating restricts circuitry created from said specific portion to said portion of said IC.
Claim 27
Dependent Claim
21 words
A digital processing system as in claim 24 wherein said IC comprises one of a programmable logic device or an ASIC.
Claim 28
Dependent Claim
22 words
A digital processing system as in claim 24 wherein said processor maps said technology independent RTL netlist to a selected technology architecture.
Claim 29
Dependent Claim
23 words
A digital processing system as in claim 26 wherein said processor maps said technology independent RTL netlist after said processor performs said allocating.
Claim 30
Dependent Claim
23 words
A digital processing system as in claim 27 wherein said processor optimizes a design of said IC after said processor performs said allocating.
Claim 31
Dependent Claim
42 words
A digital processing system as in claim 26 wherein said processor performs a place and route operation after said processor maps said technology independent RTL netlist, wherein said place and route operation creates a representation of circuitry in said selected technology architecture.
Claim 32
Dependent Claim
23 words
A digital processing system as in claim 29 wherein said processor maps said technology independent RTL netlist after said processor performs said allocating.
Claim 33
Dependent Claim
44 words
A digital processing system as in claim 30 wherein said processor maps portions of said technology independent RTL netlist to said selected technology architecture to generate estimates of IC resources and wherein said processor maps said portions after said processor compiles said HDL code.
Claim 34
Dependent Claim
25 words
A digital processing system as in claim 30 wherein said processor displays said estimates on said display device and stores said estimates in said memory.
Claim 35
Dependent Claim
54 words
A digital processing system as in claim 32 wherein said processor displays graphical representations of the area of said IC on said display device and displays on said display device representations of portions of said technology independent RTL netlist and wherein said processor performs said allocating in response to a command from a user.
Claim 36
Dependent Claim
28 words
A digital processing system as in claim 33 wherein estimates of area requirements of said portions of said technology independent RTL netlist are displayed on said display device.
Claim 37
Dependent Claim
72 words
A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method for designing an integrated circuit (IC), said method comprising: compiling an hardware description language (HDL) code to produce a technology independent RTL (register transfer level) netlist; allocating a portion of an area of said IC to a specific portion of said technology independent RTL netlist.
Claim 38
Dependent Claim
72 words
A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method for designing an integrated circuit (IC), said method comprising: compiling an hardware description language (HDL) code to produce a technology independent RTL (register transfer level) netlist; allocating a portion of an area of said IC to a specific portion of said technology independent RTL netlist.
Claim 39
Dependent Claim
24 words
A machine readable medium as in claim 35 wherein said allocating restricts circuitry created from said specific portion to said portion of said IC.
Claim 40
Dependent Claim
48 words
A machine readable medium as in claim 35 , said method further comprising: selecting logic designed for placement in one of said area of said IC and another area of said IC and replicating said logic for placement on the other of said area and said another area.
Claim 41
Dependent Claim
25 words
A machine readable medium as in claim 35 , wherein said method further comprises: mapping said technology independent RTL netlist to a selected technology architecture.
Claim 42
Dependent Claim
21 words
A machine readable medium as in claim 38 wherein said IC comprises one of a programmable logic device or an ASIC.
Claim 43
Dependent Claim
16 words
A machine readable medium as in claim 38 wherein said mapping is performed after said allocating.
Claim 44
Dependent Claim
31 words
A machine readable medium as in claim 38 , said method further comprising: performing a place and route operation after said mapping to implement said IC in said selected technology architecture.
Claim 45
Dependent Claim
19 words
A machine readable medium as in claim 38 wherein said HDL code is created without regard to said allocating.
Claim 46
Dependent Claim
26 words
A machine readable medium as in claim 38 , said method further comprising: optimizing interconnects between modules of said technology independent RTL netlist before said allocating.
Claim 47
Dependent Claim
22 words
A machine readable medium as in claim 38 , said method further comprising: optimizing a design of said IC after said allocating.
Claim 48
Dependent Claim
20 words
A machine readable medium as in claim 44 wherein said optimizing optimizes said IC by removing duplicative logic or input/outputs.
Claim 49
Dependent Claim
19 words
A machine readable medium as in claim 44 wherein said optimizing and said mapping are performed after said allocating.
Claim 50
Dependent Claim
27 words
A machine readable medium as in claim 38 , said method further comprising: partitioning said technology independent RTL netlist between representations of said IC and another IC.
Claim 51
Dependent Claim
16 words
A machine readable medium as in claim 47 wherein said partitioning is performed before said mapping.
Claim 52
Dependent Claim
43 words
A machine readable medium as in claim 47 , said method further comprising: selecting logic designed for placement on one of said IC and said another IC and replicating said logic for placement on the other of said IC and said another IC.
Claim 53
Dependent Claim
52 words
A machine readable medium as in claim 47 , said method further comprising: selecting one RTL component in said technology independent RTL netlist and splitting said one RTL component into a first RTL component designed for placement on said IC and a second RTL component designed for placement on said another IC.
Claim 54
Dependent Claim
48 words
A machine readable medium as in claim 38 herein said IC comprises a programmable logic device and wherein said method further comprises: testing a prototype of a system with said IC; performing a synthesis of said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).
Claim 55
Dependent Claim
51 words
A machine readable medium as in claim 38 , said method further comprising: mapping portions of said technology independent RTL netlist to a selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 56
Dependent Claim
20 words
A machine readable medium as in claim 52 wherein said estimates are used to decide how to perform said allocating.
Claim 57
Dependent Claim
25 words
A machine readable medium as in claim 53 wherein a user considers said estimates and selects a command to decide how to perform said allocating.
Claim 58
Independent Claim
51 words
A system for designing an integrated circuit (IC), said system comprising: means for compiling a hardware description language (HDL) code to produce a technology independent RTL (register transfer level) netlist; means for allocating a portion of an area of said IC to a specific portion of said technology independent RTL netlist.
Claim 59
Independent Claim
51 words
A system for designing an integrated circuit (IC), said system comprising: means for compiling a hardware description language (HDL) code to produce a technology independent RTL (register transfer level) netlist; means for allocating a portion of an area of said IC to a specific portion of said technology independent RTL netlist.
Claim 60
Dependent Claim
22 words
A system as in claim 55 wherein said allocating restricts circuitry created from said specific portion to said portion of said IC.
Claim 61
Dependent Claim
22 words
A system as in claim 55 further comprising: means for mapping said technology in dependent RTL netlist to a selected technology architecture.
Claim 62
Dependent Claim
19 words
A system as in claim 57 wherein said IC comprises one of a programmable logic device or an ASIC.
Claim 63
Dependent Claim
14 words
A system as in claim 57 wherein said mapping is performed after said allocating.
Claim 64
Dependent Claim
28 words
A system as in claim 57 further comprising: means for performing a place and route operation after said mapping to implement said IC in said selected technology architecture.
Claim 65
Dependent Claim
17 words
A system as in claim 57 wherein said HDL code is created without regard to said allocating.
Claim 66
Dependent Claim
48 words
A system as in claim 57 further comprising: means for mapping portions of said technology independent RTL netlist to a selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 67
Dependent Claim
18 words
A system as in claim 62 wherein said estimates are used to decide how to perform said allocating.
Claim 68
Dependent Claim
23 words
A system as in claim 63 wherein a user considers said estimates and selects a command to decide how to perform said allocating.
Claim 69
Dependent Claim
50 words
A system as in claim 57 wherein said IC comprises a programmable logic device and wherein said system further comprises: means for testing a prototype of a system with said IC; means for performing a synthesis of said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).
Claim 70
Dependent Claim
24 words
A system as in claim 57 further comprising: means for partitioning said technology independent RTL netlist between representations of said IC and another IC.
Claim 71
Dependent Claim
14 words
A system as in claim 66 wherein said partitioning is performed before said mapping.
Claim 72
Dependent Claim
40 words
A system as in claim 66 further comprising: means for selecting logic designed for placement on one of said IC and said another IC and replicating said logic for placement on the other of said IC and said another IC.
Claim 73
Dependent Claim
49 words
A system as in claim 66 further comprising: means for selecting one RTL component in said technology independent RTL netlist and splitting said one RTL component into a first RTL component designed for placement on said IC and a second RTL component designed for placement on said another IC.
Claim 74
Dependent Claim
23 words
A system as in claim 57 further comprising: means for optimizing interconnects between modules of said technology independent RTL netlist before said allocating.
Claim 75
Dependent Claim
19 words
A system as in claim 57 further comprising: means for optimizing a design of said IC after said allocating.
Claim 76
Dependent Claim
18 words
A system as in claim 71 wherein said optimizing optimizes said IC by removing duplicative logic or input/outputs.
Claim 77
Dependent Claim
17 words
A system as in claim 71 wherein said optimizing and said mapping are performed after said allocating.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-02-10 | 2006-08-12 | 2007-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-02-10 | 2010-08-12 | 2011-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-02-10 | 2014-08-12 | 2015-02-11 | $7700.00 | Window Closed / Lapsed |