US6135647A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code
Assignee: Bell Semiconductor LLC
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Filing: 1997-10-23
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Granted: 2000-10-24
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Expires: 2017-10-23
Abstract
Abstract A system and method for representing a system level RTL hardware design using an HDL independent RTL representation and translation into synthesizable RTL code. The present invention creates an object-oriented library which can be used to implement RTL hardware designs in terms of HDL independent objects. Instead of implementing multiple HDL instances of hardware modules, the invention enables software tool programmers to implement one HDL-independent instance of the hardware module. As a result, a programmer can focus his efforts on generating the functionality of the module and can be relieved from the time consuming task of generating the detailed syntax of multiple HDLs. The present invention also maintains synchronization across multiple HDLs so that a software designer can generate HDL code for any supported HDL, e.g., Verilog or VHDL, thus making software maintenance easier.
Inventors
- 👤 Arun Balakrishnan
- 👤 Kaushik De
- 👤 Jun Qian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:31
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
44 words
A method for processing a system level hardware design representation using a digital computer, the method comprising the steps of: receiving a system level hardware design representation; and transforming said system level hardware design representation into a synthesizable HDL-independent RTL representation of object-oriented components.
Claim 2
Independent Claim
44 words
A method for processing a system level hardware design representation using a digital computer, the method comprising the steps of: receiving a system level hardware design representation; and transforming said system level hardware design representation into a synthesizable HDL-independent RTL representation of object-oriented components.
Claim 3
Dependent Claim
19 words
The method of claim 1, further comprising the step of: transforming said object-oriented components into a HDL code representation.
Claim 4
Dependent Claim
19 words
The method of claim 2, further comprising the step of: outputting said HDL representation to a digital computer file.
Claim 5
Dependent Claim
19 words
The method of claim 1, further comprising the step of: transforming said object-oriented components into a Verilog code representation.
Claim 6
Dependent Claim
20 words
The method of claim 4, further comprising the step of: outputting said Verilog code representation to a digital computer file.
Claim 7
Dependent Claim
19 words
The method of claim 1, further comprising the step of: transforming said object-oriented components into a VHDL code representation.
Claim 8
Dependent Claim
20 words
The method of claim 6, further comprising the step of: outputting said VHDL code representation to a digital computer file.
Claim 9
Independent Claim
154 words
A system for generating a computer program using a digital computer, said computer program capable of transforming a system level hardware design representation into a synthesizable HDL-independent RTL representation, comprising: a processor; a storage device coupled to said processor; a user interface, coupled to said storage device or processor, for allowing a user to specify and initiate the compilation of a computer program; an objected-oriented language compiler/linker, resident in said storage device, for compiling and linking computer program source code files and computer programming library files; computer programming library files, resident in said storage device, for generating object-oriented programming objects; an object-oriented computer programming library file, resident in said storage device, for generating synthesizable HDL-independent RTL hardware design objects; and computer program source code files, resident in said storage device, said files being compilable into a computer program for receiving system level hardware design user input and translating said input into a RTL representation.
Claim 10
Independent Claim
154 words
A system for generating a computer program using a digital computer, said computer program capable of transforming a system level hardware design representation into a synthesizable HDL-independent RTL representation, comprising: a processor; a storage device coupled to said processor; a user interface, coupled to said storage device or processor, for allowing a user to specify and initiate the compilation of a computer program; an objected-oriented language compiler/linker, resident in said storage device, for compiling and linking computer program source code files and computer programming library files; computer programming library files, resident in said storage device, for generating object-oriented programming objects; an object-oriented computer programming library file, resident in said storage device, for generating synthesizable HDL-independent RTL hardware design objects; and computer program source code files, resident in said storage device, said files being compilable into a computer program for receiving system level hardware design user input and translating said input into a RTL representation.
Claim 11
Independent Claim
107 words
A system for transforming a system level hardware design into a RTL hardware design using a digital computer comprising: a processor; storage means coupled to said processor; user interfacing means coupled to said processor, disposed to receive signals from the system user representing a system level hardware design; system level hardware design receiving means, disposed to receive signals from said user interfacing means, for receiving signals indicative of the system level hardware design; and system level hardware design transforming means, coupled to said system level hardware design representation receiving means, for transforming signals indicative of the system level hardware design into a synthesizable HDL-independent RTL object-oriented representation.
Claim 12
Independent Claim
107 words
A system for transforming a system level hardware design into a RTL hardware design using a digital computer comprising: a processor; storage means coupled to said processor; user interfacing means coupled to said processor, disposed to receive signals from the system user representing a system level hardware design; system level hardware design receiving means, disposed to receive signals from said user interfacing means, for receiving signals indicative of the system level hardware design; and system level hardware design transforming means, coupled to said system level hardware design representation receiving means, for transforming signals indicative of the system level hardware design into a synthesizable HDL-independent RTL object-oriented representation.
Claim 13
Dependent Claim
33 words
The system of claim 9, further comprising: HDL code generating means, coupled to said system level hardware design transforming means, for generating a HDL code representation of a synthesizable HDL-independent RTL object-oriented representation.
Claim 14
Dependent Claim
30 words
The system of claim 10, further comprising: RTL code outputting means, coupled to said HDL code generating means, for generating a digital computer file consisting of a HDL code representation.
Claim 15
Dependent Claim
30 words
The system of claim 10, further comprising: RTL code outputting means, coupled to said HDL code generating means, for generating a digital computer file consisting of a Verilog code representation.
Claim 16
Dependent Claim
30 words
The system of claim 10, further comprising: RTL code outputting means, coupled to said HDL code generating means, for generating a digital computer file consisting of a VHDL code representation.
Claim 17
Dependent Claim
32 words
The system of claim 9, further comprising: HDL code generation means, coupled to said system level hardware design transforming means, for generating a Verilog code representation of the system level hardware design.
Claim 18
Dependent Claim
32 words
The system of claim 9, further comprising: HDL code generation means, coupled to said system level hardware design transforming means, for generating a VHDL code representation of the system level hardware design.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-24 | 2004-04-24 | 2004-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-24 | 2008-04-24 | 2008-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-24 | 2012-04-24 | 2012-10-24 | $7700.00 | Window Closed / Lapsed |