US5953235A
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Method for processing a hardware independent user description to generate logic circuit elements including flip-flops, latches, and three-state buffers and combinations thereof
Assignee: Synopsys Inc
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Filing: 1997-08-25
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Granted: 1999-09-14
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Expires: 2017-08-25
Abstract
Abstract A method and system are provided for generating a logic network using a hardware independent description means. A logic circuit synthesizer, in response to a user description specifying only signals and the circumstances under which the signals are produced, generates a logic network that generates the signals specified in the user description, e.g., a net list of logic elements, such as logic gates, high impedance drivers, level sensitive latches and edge sensitive flip-flops along with the interconnections of the logic elements. In one embodiment, the logic circuit synthesizer includes a preprocessor means and a logic circuit generator means. The preprocessor means, in response to the user description, converts signals and conditions in the user description into a structure having nodes interconnected by edges. The edges include an edge condition under which the edge is traversed. The logic circuit generator, using the structure and the edge conditions, creates a logic network that generates the signals specified in the user description.
Inventors
- 👤 Brent L. Gregory
- 👤 Russell B. Segal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:27
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
131 words
A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element comprising: converting said hardware independent user description into a graph structure in a computer memory wherein said hardware independent user desctiption includes first instructions of a form: ##EQU1## wherein signal COND is a condition; and signal Q is a logic signal that is assigned a logic value of signal D; and generating a latch having an input data line, a latch gate line, and an output line using information, generated from said first instructions, in said graph structure; wherein said signal D is on said input data line; said signal COND on said latch gate line; and said logic signal Q is on said output line.
Claim 2
Independent Claim
131 words
A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element comprising: converting said hardware independent user description into a graph structure in a computer memory wherein said hardware independent user desctiption includes first instructions of a form: ##EQU1## wherein signal COND is a condition; and signal Q is a logic signal that is assigned a logic value of signal D; and generating a latch having an input data line, a latch gate line, and an output line using information, generated from said first instructions, in said graph structure; wherein said signal D is on said input data line; said signal COND on said latch gate line; and said logic signal Q is on said output line.
Claim 3
Dependent Claim
137 words
A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element as in claim 1 wherein said hardware independent user description includes second instructions of a form: ##EQU2## wherein signal positive -- edge(CLOCK) is a condition representing a positive edge of a clock signal CLOCK; and signal B is a logic signal that is assigned a logic value of signal C; and said method further comprises: generating a D-type flip-flop having an input data line, a clock line, and an output line using information, generated from said second instructions, in said graph structure; wherein said signal C is on said input data line; said signal positive -- edge(CLOCK) is on said clock line; and said logic signal B is on said output line.
Claim 4
Dependent Claim
223 words
A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element as in claim 2 wherein said hardware independent user description includes third instructions of a form: ##EQU3## wherein signal positive -- edge (CLOCK1) is a condition representing a positive edge of a clock signal CLOCK1; signal A is a logic signal; signal "Z" is a high impedance signal; signal E is a non-constant logic signal; and said method further comprises: generating using information, generated from said third instructions, in said graph structure a second D-type flip-flop having an input data line, a clock line, and an output line; wherein said signal E is on said input data line of said second D-type flip-flop; and said signal positive -- edge(CLOCK1) is on said clock line of said second D-type flip-flop; and generating using information in said graph structure generated from said third instructions, a three state element having a data input line, an enable line, and an output line; wherein said three state element data input line is connected to output line of said second D-type flip-flop; said three state element enable line is connected to said third D-type flip-flop output line through an inverter; and said logic signal A is on said output line of said three-state element.
Claim 5
Dependent Claim
240 words
A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element as in claim 3 wherein said hardware independent user description includes fourth instructions of a form: ##EQU4## wherein signal positive -- edge(CLOCK4) is a condition representing a positive edge of a clock signal CLOCK4; signal A1 is a logic signal; signal b+c is a logic OR of non-constant logic signals b and c; and said method further comprises: generating using information, generated from said fourth instructions, in said graph structure a fourth D-type flip-flop having an input data line, a clock line, and an output line; wherein said signal positive -- edge(CLOCK4) is on said clock line of said fourth D-type flip-flop; and said signal A1 is on said output line of said fourth D-type flip-flop; generating using information, generated from said fourth instructions, in said graph structure a multiplexer having: a first input terminal connected to said output line of said fourth D-type flip-flop; a second input terminal connected to an output terminal of an OR gate wherein a first input terminal of said OR gate is connected to receive said signal b and a second input terminal of said OR gate is connected to receive said signal c; an input signal select terminal connected to said condition signal COND4; and an output terminal connected to said input line of said fourth D-type flip-flop.
Claim 6
Dependent Claim
280 words
A method for converting a hardwware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element as in claim 1 wherein said hardware independent user description includes second instructions of a form: ##EQU5## wherein signal positive -- edge(CLOCK1) is a condition representing a positive edge of a clock signal CLOCK1; signal A is a logic signal; signal "Z" is a high impedance signal; and signal E is a non-constant logic signal; and said method further comprises: generating using information, generated from said second instructions, in said graph structure a first D-type flip-flop having an input data line, a clock line, and an output line; wherein said signal E is on said input data line of said first D-type flip-flop; and said signal positive -- edge(CLOCK1) is on said clock line of said first D-type flip-flop; generating using information, generated from said second instructions, in said graph structure a first D-type flip-flop having an input data line, a clock line, and an output line; wherein said signal COND is on said input data line of said second D-type flip-flop; said signal positive -- edge(CLOCK1) is on said clock line of said second D-type flip-flop; generating, using information in said graph structure generated from said second instructions, a three state element having a data input line, an enable line, and an output line; wherein said three state element data input line is connected to output line of said first D-type flip-flop; said three state element enable line is connected to said second D-type flip-flop output line through an inverter; and said logic signal A is on said output line of said three-state element.
Claim 7
Dependent Claim
231 words
A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element as in claim 1 wherein said hardware independent user description includes second instructions of a form: ##EQU6## wherein signal positive -- edge(CLOCK4) is a condition representing a positive edge of a clock signal CLOCK4; signal A1 is a logic signal; signal b+c is a logic OR of non-constant logic signals b and c and said method further comprises: generating using information, generated from said second instructions, in said graph structure a D-type flip-flop having an input data line, a clock line, and an output line; wherein said signal positive -- edge(CLOCK4) is on said clock line of said D-type flip-flop; and said signal A1 is on said output line of said D-type flip-flop; generating using information, generated from said second instructions, in said graph structure a multiplexer having: a first terminal connected to said output line of said D-type flip-flop; a second input terminal connected of an output terminal of an OR gate wherein a first input terminal of said OR gate is connected said signal b and a second input terminal of said OR gate is connected to said signal c; an input signal select terminal connected to said condition signal COND4; and an output terminal connected to said input line of said D-type flip-flop.
Claim 8
Independent Claim
141 words
A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element comprising: converting said hardware independent user description into a graph structure in a computer memory wherein said hardware independent user description includes instructions of a form: ##EQU7## wherein signal positive -- edge(CLOCK) is a condition representing a positive edge of a clock signal CLOCK; and signal B is a logic signal that is assigned a logic value of signal C; and generating a D-type flip-flop having an input data line, a clock line, and an output line using information, generated from said instructions, in said graph structure; wherein said signal C is on said input data line; said signal positive edge(CLOCK) is on said clock line; and said logic signal B is on said output line.
Claim 9
Independent Claim
141 words
A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element comprising: converting said hardware independent user description into a graph structure in a computer memory wherein said hardware independent user description includes instructions of a form: ##EQU7## wherein signal positive -- edge(CLOCK) is a condition representing a positive edge of a clock signal CLOCK; and signal B is a logic signal that is assigned a logic value of signal C; and generating a D-type flip-flop having an input data line, a clock line, and an output line using information, generated from said instructions, in said graph structure; wherein said signal C is on said input data line; said signal positive edge(CLOCK) is on said clock line; and said logic signal B is on said output line.
Claim 10
Independent Claim
284 words
A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element comprising: converting said hardware independent user description into a graph structure in a computer memory wherein said hardware independent user description includes instructions of a form: ##EQU8## wherein signal positive -- edge(CLOCK1) is a condition representing a positive edge of a clock signal CLOCK1; signal A is a logic signal; signal "Z" is a high impedance signal; and signal E is a non-constant logic signal; and generating using information, generated from said instructions, in said graph structure a first D-type flip-flop having an input data line, a clock line, and an output line; wherein said signal E is on said input data line of said first D-type flip-flop; and said signal positive -- edge(CLOCK1) is on said clock line of said first D-type flip-flop; generating using information, generated from said instructions, in said graph structure a second D-type flip-flop having an input data line, a clock line, and an output line; wherein said signal COND is on said input data line of said second D-type flip-flop; said signal positive -- edge(CLOCK1) is on said clock line of said second D-type flip-flop; and generating, using information in said graph structure generated from said instructions, a three state element having a data input line, an enable line, and an output line; wherein said three state element data input line is connected to output line of said first D-type flip-flop; said three state element enable line is connected to said second D-type flip-flop output line through an inverter; and said logic signal A is on said output line of said three-state element.
Claim 11
Independent Claim
284 words
A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element comprising: converting said hardware independent user description into a graph structure in a computer memory wherein said hardware independent user description includes instructions of a form: ##EQU8## wherein signal positive -- edge(CLOCK1) is a condition representing a positive edge of a clock signal CLOCK1; signal A is a logic signal; signal "Z" is a high impedance signal; and signal E is a non-constant logic signal; and generating using information, generated from said instructions, in said graph structure a first D-type flip-flop having an input data line, a clock line, and an output line; wherein said signal E is on said input data line of said first D-type flip-flop; and said signal positive -- edge(CLOCK1) is on said clock line of said first D-type flip-flop; generating using information, generated from said instructions, in said graph structure a second D-type flip-flop having an input data line, a clock line, and an output line; wherein said signal COND is on said input data line of said second D-type flip-flop; said signal positive -- edge(CLOCK1) is on said clock line of said second D-type flip-flop; and generating, using information in said graph structure generated from said instructions, a three state element having a data input line, an enable line, and an output line; wherein said three state element data input line is connected to output line of said first D-type flip-flop; said three state element enable line is connected to said second D-type flip-flop output line through an inverter; and said logic signal A is on said output line of said three-state element.
Claim 12
Independent Claim
237 words
A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element comprising: converting said hardware independent user description into a graph structure in a computer memory wherein said hardware independent user description includes instructions of a form: ##EQU9## wherein signal positive -- edge(CLOCK4) is a condition representing a positive edge of a clock signal CLOCK4; signal A1 is a logic signal; signal b+c is a logic OR of non-constant logic signals b and c; and generating using information, generated from said fourth instructions, in said graph structure a D-type flip-flop having an input data line, a clock line, and an output line; wherein said signal positive -- edge(CLOCK4) is on said clock line of said D-type flip-flop; and said signal A1 is on said output line of said D-type flip-flop; and generating using information, generated from said instructions, in said graph structure a multiplexer having: a first terminal connected to said output line of said D-type flip-flop; a second input terminal connected of an output terminal of an OR gate wherein a first input terminal of said OR gate is connected said signal b and a second input terminal of said OR gate is connected to said signal c; an input signal select terminal connected to said condition signal COND4; and an output terminal connected to said input line of said D-type flip-flop.
Claim 13
Independent Claim
237 words
A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element comprising: converting said hardware independent user description into a graph structure in a computer memory wherein said hardware independent user description includes instructions of a form: ##EQU9## wherein signal positive -- edge(CLOCK4) is a condition representing a positive edge of a clock signal CLOCK4; signal A1 is a logic signal; signal b+c is a logic OR of non-constant logic signals b and c; and generating using information, generated from said fourth instructions, in said graph structure a D-type flip-flop having an input data line, a clock line, and an output line; wherein said signal positive -- edge(CLOCK4) is on said clock line of said D-type flip-flop; and said signal A1 is on said output line of said D-type flip-flop; and generating using information, generated from said instructions, in said graph structure a multiplexer having: a first terminal connected to said output line of said D-type flip-flop; a second input terminal connected of an output terminal of an OR gate wherein a first input terminal of said OR gate is connected said signal b and a second input terminal of said OR gate is connected to said signal c; an input signal select terminal connected to said condition signal COND4; and an output terminal connected to said input line of said D-type flip-flop.
References Cited (Backward Citations)
US5661661A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-13 | 2003-03-15 | 2003-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-13 | 2007-03-15 | 2007-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-13 | 2011-03-15 | 2011-09-14 | $7700.00 | Window Closed / Lapsed |