Patent US6657634B1 successfully refreshed from Google Patents.
US6657634B1
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Dynamic graphics and/or video memory power reducing circuit and method
Assignee: Advanced Silicon Technologies LLC
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Filing: 1999-02-25
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Granted: 2003-12-02
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Expires: 2019-02-25
Abstract
Abstract An apparatus and method dynamically controls the graphics and/or video memory power dynamically during idle periods of the memory interface during active system modes. In one embodiment, a memory request detector generates memory request indication data, such as data representing whether memory requests have been received within a predetermined time, based on detection of graphics and/or video memory requests during an active mode of the display system operation. A dynamic activity based memory power controller analyzes the memory request indication data and controls the power consumption of the graphics and/or video memory based on whether memory requests are detected.
Inventors
- 👤 David E. Sinclair
- 👤 Eric Young
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:18
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/3218; G06F1/3234; G06F1/325; G06F1/3265; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G09; G09G; G09G5/00; G09G5/36; G09G5/363; G09G2330/00; G09G2330/02; G09G2330/021; G09G2330/022; Y; Y02; Y02D; Y02D10/00; Y02D30/00; Y02D30/50
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
81 words
A dynamic graphics and/or video memory power consumption reducing circuit comprising: at least one memory request detector that generates memory request indication data based on detection of graphics and/or video memory requests in a graphics processing subsystem; and at least one dynamic memory activity based power controller, operatively responsive to the memory request indication data, operative to control power consumption of the graphics and/or video memory based on whether graphics and/or video memory requests are detected within a predetermined time period.
Claim 2
Dependent Claim
81 words
A dynamic graphics and/or video memory power consumption reducing circuit comprising: at least one memory request detector that generates memory request indication data based on detection of graphics and/or video memory requests in a graphics processing subsystem; and at least one dynamic memory activity based power controller, operatively responsive to the memory request indication data, operative to control power consumption of the graphics and/or video memory based on whether graphics and/or video memory requests are detected within a predetermined time period.
Claim 3
Dependent Claim
33 words
The circuit of claim 1 wherein the dynamic memory activity based power controller reduces power consumption of the graphics and/or video memory based on inactivity of memory requests within the predetermined time period.
Claim 4
Dependent Claim
35 words
The circuit of claim 2 wherein the dynamic memory activity based power controller controls a memory clock enable signal of the graphics and/or video memory to reduce power consumption of the graphics and/or video memory.
Claim 5
Dependent Claim
24 words
The circuit of claim 1 wherein the memory request detector directly detects memory requests from a memory request generator or indirectly detects memory requests.
Claim 6
Dependent Claim
30 words
The circuit of claim 1 including control logic operatively responsive to the memory request indication data for indicating whether to reduce power consumption based on the memory request indication data.
Claim 7
Dependent Claim
41 words
The circuit of claim 1 wherein the at least one memory request detector generates memory request indication data based on detection of graphics and/or video memory requests for a plurality of memories each containing at least graphics data and/or video data.
Claim 8
Dependent Claim
33 words
The circuit of claim 5 wherein the control logic includes a programmable timer that is updated during memory request inactivity and reset based on memory request activity to calculate the predetermined time period.
Claim 9
Dependent Claim
48 words
The circuit of claim 1 wherein the memory request detector is operatively coupled to a request arbitor that arbitrates among a plurality of graphics and/or video memory requests prior to the memory request detector generating memory request indication data based on detection of graphics and/or video memory requests.
Claim 10
Dependent Claim
31 words
The circuit of claim 1 wherein the memory request detector and the dynamic memory activity based power controller are part of a display data memory controller in a graphics processing system.
Claim 11
Dependent Claim
58 words
A dynamic graphics and/or video memory power consumption method comprising the steps of: generating memory request indication data based on detection of graphics and/or video memory request activity in a graphics processing subsystem; and controlling power consumption of the graphics and/or video memory based on whether graphics and/or video memory requests are detected within a predetermined time period.
Claim 12
Dependent Claim
58 words
A dynamic graphics and/or video memory power consumption method comprising the steps of: generating memory request indication data based on detection of graphics and/or video memory request activity in a graphics processing subsystem; and controlling power consumption of the graphics and/or video memory based on whether graphics and/or video memory requests are detected within a predetermined time period.
Claim 13
Dependent Claim
26 words
The method of claim 10 including reducing power consumption of the graphics and/or video memory based on inactivity of memory requests within the predetermined time period.
Claim 14
Dependent Claim
35 words
The method of claim 11 wherein the step of reducing power consumption includes controlling a memory clock enable signal of the graphics and/or video memory to reduce power consumption of the graphics and/or video memory.
Claim 15
Dependent Claim
25 words
The method of claim 10 wherein the step of detection includes directly detecting memory requests from a memory request generator or indirectly detecting memory requests.
Claim 16
Dependent Claim
34 words
The method of claim 10 including generating memory request indication data based on detection of graphics and/or video memory requests for a plurality of memories each containing at least graphics data and/or video data.
Claim 17
Dependent Claim
30 words
The method of claim 10 including updating a programmable timer that is updated during memory request inactivity and reset based on memory request activity to calculate the predetermined time period.
Claim 18
Dependent Claim
32 words
The method of claim 10 wherein the step of detection includes detecting a static display screen condition to facilitate reduced power consumption of graphics and/or video memory in the graphics processing subsystem.
Claim 19
Dependent Claim
39 words
The method of claim 10 including the step of arbitrating among a plurality of graphics and/or video memory requests prior to a memory request detector generating memory request indication data based on detection of graphics and/or video memory requests.
Claim 20
Dependent Claim
127 words
A dynamic graphics and/or video memory power consumption reducing circuit comprising: at least one memory request detector that generates memory request indication data based on detection of graphics and/or video memory requests, wherein the memory request detector detects a static display screen condition to facilitate reduced power consumption of graphics and/or video memory in a graphics processing subsystem; and at least one dynamic memory activity based power controller, operatively responsive to the memory request indication data, having control logic operative to control power consumption of the graphics and/or video memory based on whether graphics and/or video memory requests are detected within a predetermined time period, wherein the control logic includes a programmable timer that is updated during memory request inactivity and reset based on memory request activity.
Claim 21
Dependent Claim
127 words
A dynamic graphics and/or video memory power consumption reducing circuit comprising: at least one memory request detector that generates memory request indication data based on detection of graphics and/or video memory requests, wherein the memory request detector detects a static display screen condition to facilitate reduced power consumption of graphics and/or video memory in a graphics processing subsystem; and at least one dynamic memory activity based power controller, operatively responsive to the memory request indication data, having control logic operative to control power consumption of the graphics and/or video memory based on whether graphics and/or video memory requests are detected within a predetermined time period, wherein the control logic includes a programmable timer that is updated during memory request inactivity and reset based on memory request activity.
Claim 22
Dependent Claim
41 words
The circuit of claim 18 wherein the at least one memory request detector generates memory request indication data based on detection of graphics and/or video memory requests for a plurality of memories each containing at least graphics data and/or video data.
Claim 23
Dependent Claim
48 words
The circuit of claim 18 wherein the memory request detector is operatively coupled to a request arbitor that arbitrates among a plurality of graphics and/or video memory requests prior to the memory request detector generating memory request indication data based on detection of graphics and/or video memory requests.
Claim 24
Dependent Claim
31 words
The circuit of claim 20 wherein the memory request detector and the dynamic memory activity based power controller are part of a display data memory controller in a graphics processing system.
Claim 25
Dependent Claim
66 words
A dynamic memory power consumption reducing circuit, comprising: a memory request detector operative to generate memory request indication data based on detection of frame buffer memory requests; and a dynamic memory based power controller, operatively responsive to the memory request indication data, to control power consumption of frame buffer memory during system active modes based on the memory request indication data within a predetermined time period.
Claim 26
Dependent Claim
66 words
A dynamic memory power consumption reducing circuit, comprising: a memory request detector operative to generate memory request indication data based on detection of frame buffer memory requests; and a dynamic memory based power controller, operatively responsive to the memory request indication data, to control power consumption of frame buffer memory during system active modes based on the memory request indication data within a predetermined time period.
Claim 27
Dependent Claim
17 words
The circuit of claim 22 , wherein the frame buffer memory further includes graphics and/or video memory.
Claim 28
Dependent Claim
33 words
The circuit of claim 22 , wherein the dynamic memory based power controller controls a memory clock enable signal of the frame buffer memory to reduce power consumption of the frame buffer memory.
Claim 29
Dependent Claim
24 words
The circuit of claim 22 , wherein the memory request detector detects memory requests from a memory request generator or indirectly detects memory requests.
Claim 30
Dependent Claim
32 words
The circuit of claim 22 , further including control logic operatively responsive to the memory request indication data for indicating whether to reduce power consumption based on the memory request indication data.
Claim 31
Dependent Claim
30 words
The circuit of claim 26 , wherein the control logic includes a programmable timer that is updated during memory request inactivity and reset based on frame buffer memory request activity.
Claim 32
Dependent Claim
47 words
The circuit of claim 22 , further including a request arbitor, operatively coupled to the memory request detector, to arbitrate among a plurality of frame buffer memory requests prior to the memory request detector generating memory request indication data based on detection of frame buffer memory requests.
Claim 33
Dependent Claim
63 words
A graphics and/or video memory power consumption reducing circuit, comprising: a memory request detector operative to generate request indication data based on detection of graphics and/or memory requests from at least one request engine; and a power controller, operative to power down the entire graphics and/or video memory based on whether graphics and/or video memory requests are detected within a predetermined time period.
Claim 34
Dependent Claim
63 words
A graphics and/or video memory power consumption reducing circuit, comprising: a memory request detector operative to generate request indication data based on detection of graphics and/or memory requests from at least one request engine; and a power controller, operative to power down the entire graphics and/or video memory based on whether graphics and/or video memory requests are detected within a predetermined time period.
Claim 35
Dependent Claim
56 words
The graphics and/or video memory power consumption reducing circuit of claim 29 , wherein the graphics and/or frame buffer memory includes a frame buffer memory, and further including control logic operatively responsive to the memory request indication data for indicating whether to power down the graphics and/or video memory based on the memory request indication data.
Claim 36
Dependent Claim
37 words
The graphics and/or video memory power consumption reducing circuit of claim 30 , wherein the control logic includes a programmable timer that is updated during memory request inactivity and reset based on frame buffer memory request activity.
Claim 37
Dependent Claim
54 words
The graphics and/or video memory power consumption reducing circuit of claim 29 , further including a request arbitor, operatively coupled to the memory request detector, to arbitrate among a plurality of frame buffer memory requests prior to the memory request detector generating memory request indication data based on detection of frame buffer memory requests.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-12-01 | 2007-06-02 | 2007-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-12-01 | 2011-06-02 | 2011-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-12-01 | 2015-06-02 | 2015-12-02 | $7700.00 | Window Closed / Lapsed |