US6636996B2 — Method and apparatus for testing pipelined dynami…

Claim 1

Independent Claim 76 words

An integrated circuit comprising: a tester interface; a dynamic logic pipeline; an input scan latch coupled to said tester interface configured to hold a value loadable into a dynamic logic gate within said dynamic logic pipeline; and a scan ladder coupled to an evaluation node of said dynamic logic gate and further coupled to a load clock of said tester interface, such that said scan ladder may discharge said evaluation node in conformity with said value.

Claim 2

Dependent Claim 76 words

An integrated circuit comprising: a tester interface; a dynamic logic pipeline; an input scan latch coupled to said tester interface configured to hold a value loadable into a dynamic logic gate within said dynamic logic pipeline; and a scan ladder coupled to an evaluation node of said dynamic logic gate and further coupled to a load clock of said tester interface, such that said scan ladder may discharge said evaluation node in conformity with said value.

Claim 3

Dependent Claim 37 words

The integrated circuit of claim 1 , wherein said scan ladder comprises a first transistor having a gate coupled to an output of said input scan latch and a first channel connection coupled to said evaluation node.

Claim 4

Dependent Claim 49 words

The integrated circuit of claim 2 , wherein said scan ladder further comprises a second transistor having a gate coupled to said load clock, a first channel connection coupled to a second channel connection of said first transistor and a second channel connection coupled to a power supply rail.

Claim 5

Dependent Claim 53 words

The integrated circuit of claim 1 , further comprising: an output scan latch for latching a result of the propagation of said value through said dynamic logic pipeline; and a dynamic inverter having an input coupled to an output of said dynamic logic pipeline and a clock input for presetting said dynamic inverter.

Claim 6

Dependent Claim 41 words

The integrated circuit of claim 4 , further comprising a delayed one-shot circuit for clocking said clock input of said dynamic inverter, wherein said delayed one-shot is coupled to a stop control output of said tester interface for latching said result.

Claim 7

Dependent Claim 54 words

The integrated circuit of claim 5 , further comprising: an input scan latch for latching a second value for loading into a first stage of said dynamic logic pipeline; and a dynamic inverter having an input coupled to an output of said input scan latch and a clock input for presetting said dynamic inverter.

Claim 8

Dependent Claim 45 words

The integrated circuit of claim 6 , further comprising a delayed one-shot circuit for clocking said clock input of said dynamic inverter, wherein said delayed one-shot is coupled to said load clock for clocking said second value into said first stage of said dynamic pipeline.

Claim 9

Dependent Claim 54 words

The integrated circuit of claim 1 , further comprising: an input scan latch for latching a second value for loading into a first stage of said dynamic logic pipeline; and a dynamic inverter having an input coupled to an output of said input scan latch and a clock input for presetting said dynamic inverter.

Claim 10

Dependent Claim 45 words

The integrated circuit of claim 8 , further comprising a delayed one-shot circuit for clocking said clock input of said dynamic inverter, wherein said delayed one-shot is coupled to said load clock for clocking said second value into said first stage of said dynamic pipeline.

Claim 11

Dependent Claim 75 words

A dynamic logic gate, comprising: a preset device coupled to an evaluation node of said dynamic logic gate for charging said evaluation node to a preset state; a logic input ladder coupled to said evaluation node for discharging said evaluation node in conformity with a state of logic inputs; and a scan ladder coupled to said evaluation node, said scan ladder having an input for coupling a load clock for testing said dynamic logic gate.

Claim 12

Dependent Claim 75 words

A dynamic logic gate, comprising: a preset device coupled to an evaluation node of said dynamic logic gate for charging said evaluation node to a preset state; a logic input ladder coupled to said evaluation node for discharging said evaluation node in conformity with a state of logic inputs; and a scan ladder coupled to said evaluation node, said scan ladder having an input for coupling a load clock for testing said dynamic logic gate.

Claim 13

Dependent Claim 41 words

The dynamic logic gate of claim 10 , wherein said logic input ladder comprises a functional foot device coupled to a functional logic clock for enabling said logic input ladder when said dynamic logic gate is operated in a functional mode.

Claim 14

Dependent Claim 40 words

The dynamic logic gate of claim 10 , wherein said data load ladder comprises a test foot device coupled to said load clock for enabling said logic input ladder when said dynamic logic gate is operated in a test mode.

Claim 15

Dependent Claim 27 words

The dynamic logic gate of claim 12 , wherein said test foot device is enabled once for a transition from a scan mode to a functional mode.

Claim 16

Dependent Claim 41 words

The dynamic logic gate of claim 12 , wherein said logic input ladder comprises a functional foot device coupled to a functional logic clock for enabling said logic input ladder when said dynamic logic gate is operated in a functional mode.

Claim 17

Independent Claim 77 words

A method for testing pipelined dynamic logic within an integrated circuit, said method comprising the steps of: loading a value into a scan latch from a scan chain; presetting an evaluation node within said dynamic logic; determining whether or not said integrated circuit is transitioning from scan mode to functional mode; and in response to determining that said integrated circuit is transitioning from scan mode to functional mode, discharging said evaluation node in conformity with said value.

Claim 18

Independent Claim 77 words

A method for testing pipelined dynamic logic within an integrated circuit, said method comprising the steps of: loading a value into a scan latch from a scan chain; presetting an evaluation node within said dynamic logic; determining whether or not said integrated circuit is transitioning from scan mode to functional mode; and in response to determining that said integrated circuit is transitioning from scan mode to functional mode, discharging said evaluation node in conformity with said value.

Claim 19

Dependent Claim 21 words

The method of claim 15 , wherein said step of determining disables a functional logic clock associated with said evaluation node.

Claim 20

Dependent Claim 21 words

The method of claim 16 , wherein said step of disabling a functional logic clock further disables a logic input ladder.

Claim 21

Dependent Claim 22 words

The method of claim 16 , wherein said step of discharging is performed by enabling a scan ladder controlled by said value.

Claim 22

Dependent Claim 27 words

The method of claim 18 , wherein said step of enabling is performed by a load clock for loading values into functional logic from said scan chain.

Claim 23

Dependent Claim 32 words

The method of claim 19 , wherein said load clock is a scan clock controlling clocking of master latches within said integrated circuit and wherein said scan clock enables said scan ladder.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2006-10-20	2007-04-21	2007-10-21	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2010-10-20	2011-04-21	2011-10-21	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2014-10-20	2015-04-21	2015-10-21	$7700.00	Window Closed / Lapsed

Method and apparatus for testing pipelined dynamic logic

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