US5859547A
Expired / Lapsed
US
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Dynamic logic circuit
Assignee: AVM TECHNOLOGIES LLC
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Filing: 1996-12-20
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Granted: 1999-01-12
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Expires: 2016-12-20
Abstract
Abstract A dynamic logic circuit that uses substantially constant power and that has substantially constant propagation delay, independent of the number of inputs the dynamic logic circuit contains. In one embodiment of the circuit, an evaluation transistor is positioned between a precharge transistor and a dynamic logic block. The evaluation transistor separates a precharge node from the logic block during a precharge clock phase so that the logic block is not charged. A delay coupled to the precharge transistor allows the precharge transistor to remain activated during a portion of an evaluation clock phase to overcome any effects of charge-sharing between the precharge node and the dynamic logic block. Because the evaluation transistor separates the logic block from the precharge node, the precharge node can be charged independently of the number of inputs present in the dynamic logic block.
Inventors
- 👤 Dzung Joseph Tran
- 👤 Mark Warren Acuff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 10:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
40 words
A dynamic logic circuit, comprising: a dynamic logic block; a precharge transistor; an evaluation transistor between the dynamic logic block and the precharge transistor; and a delay coupled to the precharge transistor for simultaneously activating the precharge and evaluation transistors.
Claim 2
Dependent Claim
40 words
A dynamic logic circuit, comprising: a dynamic logic block; a precharge transistor; an evaluation transistor between the dynamic logic block and the precharge transistor; and a delay coupled to the precharge transistor for simultaneously activating the precharge and evaluation transistors.
Claim 3
Dependent Claim
30 words
The dynamic logic circuit of claim 1 wherein the precharge transistor includes a gate and a source-to-drain path, and the delay is coupled to the gate of the precharge transistor.
Claim 4
Dependent Claim
15 words
The dynamic logic circuit of claim 2 wherein the delay includes at least one inverter.
Claim 5
Dependent Claim
16 words
The dynamic logic circuit of claim 1 including an anti-float circuit coupled to the precharge transistor.
Claim 6
Dependent Claim
14 words
The dynamic logic circuit of claim 4 wherein the anti-float circuit includes a latch.
Claim 7
Dependent Claim
100 words
The dynamic logic circuit of claim 1 wherein the precharge and evaluation transistors each include a gate and a source-to-drain path, and the dynamic logic circuit includes a clock signal node coupled to the gates of the precharge and evaluation transistors for receiving a clock signal having precharge and evaluation phases for switching the precharge transistor between an active state during the precharge phase and an inactive state during a major portion of the evaluation phase and for switching the evaluation transistor between an inactive state during the precharge clock phase and an active state during the evaluation clock phase.
Claim 8
Dependent Claim
24 words
The dynamic logic circuit of claim 6 wherein the delay is coupled between the clock signal node and the gate of the precharge transistor.
Claim 9
Dependent Claim
23 words
The dynamic logic circuit of claim 1 wherein the precharge transistor is an N-channel transistor and the evaluation transistor is a P-channel transistor.
Claim 10
Dependent Claim
23 words
The dynamic logic circuit of claim 1 wherein the precharge transistor is a P-channel transistor and the evaluation transistor is an N-channel transistor.
Claim 11
Dependent Claim
35 words
The dynamic logic circuit of claim 1 wherein the dynamic logic block includes input transistors for receiving input signals and the dynamic logic circuit uses substantially constant power independent of the number of input transistors.
Claim 12
Dependent Claim
37 words
The dynamic logic circuit of claim 1 wherein the dynamic logic block includes input transistors for receiving input signals and the dynamic logic circuit has a substantially constant propagation delay independent of the number of input transistors.
Claim 13
Dependent Claim
112 words
A dynamic logic circuit, comprising: a precharge transistor including a gate terminal and a source-to-drain path coupled between a first-supply-voltage node and a precharge node; a logic block including at least one transistor coupled between a second-supply-voltage node and a logic-block output node, said at least one transistor in the logic block further including a gate terminal couplable to an input signal; an evaluation transistor having a source-to-drain path and a gate terminal, the source-to-drain path coupled between the logic-block output node and the precharge node, the gate terminal coupled to a clock signal node; and a delay coupled between the clock signal node and the gate terminal of the precharge transistor.
Claim 14
Dependent Claim
112 words
A dynamic logic circuit, comprising: a precharge transistor including a gate terminal and a source-to-drain path coupled between a first-supply-voltage node and a precharge node; a logic block including at least one transistor coupled between a second-supply-voltage node and a logic-block output node, said at least one transistor in the logic block further including a gate terminal couplable to an input signal; an evaluation transistor having a source-to-drain path and a gate terminal, the source-to-drain path coupled between the logic-block output node and the precharge node, the gate terminal coupled to a clock signal node; and a delay coupled between the clock signal node and the gate terminal of the precharge transistor.
Claim 15
Dependent Claim
49 words
The dynamic logic circuit of claim 12 further including a clock signal coupled to the clock signal node, the clock signal having a precharge phase during which the precharge transistor is activated and the evaluation transistor is deactivated and an evaluation phase during which the evaluation transistor is activated.
Claim 16
Dependent Claim
28 words
The dynamic logic circuit of claim 12, further including coupling a positive supply voltage to the first-supply voltage node and a negative supply voltage to the second-supply-voltage node.
Claim 17
Dependent Claim
27 words
The dynamic logic circuit of claim 12, further including coupling a positive supply voltage to the second-supply-voltage node and a negative supply voltage to the first-supply-voltage node.
Claim 18
Dependent Claim
17 words
The dynamic logic circuit of claim 12 further including an anti-float circuit coupled to the precharge node.
Claim 19
Dependent Claim
23 words
The dynamic logic circuit of claim 12 wherein the precharge transistor is an N-channel transistor and the evaluation transistor is a P-channel transistor.
Claim 20
Dependent Claim
23 words
The dynamic logic circuit of claim 12 wherein the precharge transistor is a P-channel transistor and the evaluation transistor is an N-channel transistor.
Claim 21
Dependent Claim
92 words
A dynamic logic circuit, comprising: a dynamic logic block having a plurality of input transistors, the arrangement of the input transistors determining the logic function of the circuit; a precharge transistor for precharging an output of the dynamic logic circuit to a first voltage level during a precharge phase; an evaluation transistor between the dynamic logic block and the precharge transistor for allowing charge sharing between the output of the dynamic logic circuit and the dynamic logic block; and the precharge and evaluation transistors are activated simultaneously for a period of time.
Claim 22
Dependent Claim
92 words
A dynamic logic circuit, comprising: a dynamic logic block having a plurality of input transistors, the arrangement of the input transistors determining the logic function of the circuit; a precharge transistor for precharging an output of the dynamic logic circuit to a first voltage level during a precharge phase; an evaluation transistor between the dynamic logic block and the precharge transistor for allowing charge sharing between the output of the dynamic logic circuit and the dynamic logic block; and the precharge and evaluation transistors are activated simultaneously for a period of time.
Claim 23
Dependent Claim
95 words
The dynamic logic circuit of claim 19 wherein the precharge transistor is responsive to a clock signal for switching between an active state during a precharge clock phase and an inactive state during a majority of the evaluation clock phase; the evaluation transistor responsive to the clock signal for switching between an inactive state during the precharge clock phase and an active state during the evaluation clock phase; and wherein the precharge transistor is active during a period of time at a beginning of the evaluation clock phase sufficient for charging the dynamic logic block.
Claim 24
Independent Claim
93 words
A method of precharging and evaluating a dynamic logic circuit, the method comprising the steps of: switching a precharge transistor, using a clock signal, between an active state during a precharge clock phase and an inactive state during a major portion of an evaluation clock phase; switching an evaluation transistor between an inactive state during the precharge clock phase and an active state during the evaluation clock phase; delaying the precharge clock phase to the precharge transistor so that the precharge transistor is activated during a minor portion of the evaluation clock phase.
Claim 25
Independent Claim
93 words
A method of precharging and evaluating a dynamic logic circuit, the method comprising the steps of: switching a precharge transistor, using a clock signal, between an active state during a precharge clock phase and an inactive state during a major portion of an evaluation clock phase; switching an evaluation transistor between an inactive state during the precharge clock phase and an active state during the evaluation clock phase; delaying the precharge clock phase to the precharge transistor so that the precharge transistor is activated during a minor portion of the evaluation clock phase.
Claim 26
Dependent Claim
74 words
A dynamic logic circuit, comprising: a dynamic logic block having input transistors all coupled in parallel; a precharge transistor; an evaluation transistor between the dynamic logic block and the precharge transistor; a clock signal node directly connected to the evaluation transistor for switching the evaluation transistor between active and inactive states; and a delay coupled to the precharge transistor for delaying the clock signal to the precharge transistor with respect to the evaluation transistor.
Claim 27
Dependent Claim
74 words
A dynamic logic circuit, comprising: a dynamic logic block having input transistors all coupled in parallel; a precharge transistor; an evaluation transistor between the dynamic logic block and the precharge transistor; a clock signal node directly connected to the evaluation transistor for switching the evaluation transistor between active and inactive states; and a delay coupled to the precharge transistor for delaying the clock signal to the precharge transistor with respect to the evaluation transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |