US6628551B2
Expired / Lapsed
US
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Reducing leakage current in memory cells
Assignee: Infineon Technologies AG
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Filing: 2001-05-14
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Granted: 2003-09-30
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Expires: 2021-05-14
Abstract
Abstract A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The access transistors are high gate threshold voltage transistors to reduce leakage current in the memory cell. The gate threshold voltage of the access transistors are, for example, 0.1 to 0.4V higher than typical transistors. Reducing leakage current advantageously improves the retention time of the memory cell.
Inventors
- 👤 Raj Kumar Jain
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:33
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/404; G11C11/406; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; H; H10; H10B; H10B10/00; H10B12/00; H10B12/01; H10B12/02; H10B12/05
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
128 words
A memory cell comprising: first and second high gate threshold voltage access transistors, each with a gate and first and second terminals, wherein the high gate threshold voltage transistors reduce leakage current through channels of the access transistors; first and second bit lines, the first bit line coupled to the first terminal of the first access transistor and the second bit line coupled to the first terminal of the second access transistor; first and second word lines, the first word line coupled to the first access transistor and the second word line coupled to the second access transistor; and a storage transistor having a gate and first and second terminals, the first and second terminals respectively coupled to the second terminals of the first and second access transistors.
Claim 2
Dependent Claim
128 words
A memory cell comprising: first and second high gate threshold voltage access transistors, each with a gate and first and second terminals, wherein the high gate threshold voltage transistors reduce leakage current through channels of the access transistors; first and second bit lines, the first bit line coupled to the first terminal of the first access transistor and the second bit line coupled to the first terminal of the second access transistor; first and second word lines, the first word line coupled to the first access transistor and the second word line coupled to the second access transistor; and a storage transistor having a gate and first and second terminals, the first and second terminals respectively coupled to the second terminals of the first and second access transistors.
Claim 3
Dependent Claim
24 words
The memory cell of claim 1 wherein a gate threshold voltage of the high gate threshold voltage transistor is increased by about 0.1-0.4 V.
Claim 4
Dependent Claim
24 words
The memory cell of claim 1 wherein a gate threshold voltage of the high gate threshold voltage transistor is increased by about 0.3-0.4 V.
Claim 5
Dependent Claim
14 words
The memory cell of claim 2 wherein the storage transistor comprises an increased capacitance.
Claim 6
Dependent Claim
14 words
The memory cell of claim 1 wherein the storage transistor comprises an increased capacitance.
Claim 7
Dependent Claim
19 words
The memory cell of claim 5 wherein the high gate threshold voltage transistor comprises an increased gate threshold voltage.
Claim 8
Dependent Claim
24 words
The memory cell of claim 6 wherein the gate threshold voltage of the high gate threshold voltage transistor is increased by about 0.1-0.4 V.
Claim 9
Dependent Claim
24 words
The memory cell of claim 6 wherein the gate threshold voltage of the high gate threshold voltage transistor is increased by about 0.3-0.4 V.
Claim 10
Dependent Claim
56 words
The memory cell of claim 6 wherein the high gate threshold voltage transistor comprises an increased gate threshold voltage, the increased, gate threshold voltage comprises either increasing the thickness of the gate dielectric of the high gate threshold transistors, tailoring the dopant profile in channels of the high gate threshold voltage transistors, or a combination thereof.
Claim 11
Dependent Claim
24 words
The memory cell of claim 9 wherein the gate threshold voltage of the high gate threshold voltage transistor is increased by about 0.1-0.4 V.
Claim 12
Dependent Claim
24 words
The memory cell of claim 9 wherein the gate threshold voltage of the high gate threshold voltage transistor is increased by about 0.3-0.4 V.
Claim 13
Dependent Claim
19 words
The memory cell of claim 1 wherein the high gate threshold voltage transistor comprises an increased gate threshold voltage.
Claim 14
Dependent Claim
24 words
The memory cell of claim 12 wherein the gate threshold voltage of the high gate threshold voltage transistor is increased by about 0.1-0.4 V.
Claim 15
Dependent Claim
24 words
The memory cell of claim 12 wherein the gate threshold voltage of the high gate threshold voltage transistor is increased by about 0.3-0.4 V.
Claim 16
Dependent Claim
56 words
The memory cell of claim 1 wherein the high gate threshold voltage transistor comprises an increased gate threshold voltage, the increased gate threshold voltage comprises either increasing the thickness of the gate dielectric of the high gate threshold transistors, tailoring the dopant profile in channels of the high gate threshold voltage transistors, or a combination thereof.
Claim 17
Dependent Claim
24 words
The memory cell of claim 15 wherein the gate threshold voltage of the high gate threshold voltage transistor is increased by about 0.1-0.4 V.
Claim 18
Dependent Claim
24 words
The memory cell of claim 15 wherein the gate threshold voltage of the high gate threshold voltage transistor is increased by about 0.3-0.4 V.
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