US6301146B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Static random access memory (RAM) systems and storage cell for same
Assignee: Oracle America Inc
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Filing: 1999-12-23
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Granted: 2001-10-09
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Expires: 2019-12-23
Abstract
Abstract A method of continuously replenishing a four-transistor static RAM storage cell is described. Such method comprises biasing both the back gate terminals and the normal gate terminals of the two bit line coupling transistors in the static RAM storage cell to voltage levels for causing a flow of small compensating currents through such coupling transistors when they are in a standby or non-access condition. Such small compensating currents are supplied to the two storage transistors in the storage cell for replenishing leakage of charge from the parasitic capacitance in the storage cell. The bias voltages arc supplied by adaptive bias circuits which adjust the bias voltages to track changes in the leakage of charge from the parasitic cell capacitance.
Inventors
- 👤 Michael Anthony Ang
- 👤 Raymond A. Heald
- 👤 Roger Y. Lo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:34
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/08; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/413; G11C11/417
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
113 words
An adaptive bias circuit for producing a bias voltage for storage cells formed on a semiconductor substrate, the bias circuit comprising: first and second field-effect transistors of opposite channel type formed on the same substrate as the storage cells, the transistors being connected in series with one another and being connected to an adaptive voltage source having a voltage value equal to the average bit line voltage of a selected group of the storage cells; and an amplifier circuit formed on the same substrate as the storage cells and having an input connected to the junction between the transistors and having an output for providing an adaptive bias voltage for the storage cells.
Claim 2
Dependent Claim
113 words
An adaptive bias circuit for producing a bias voltage for storage cells formed on a semiconductor substrate, the bias circuit comprising: first and second field-effect transistors of opposite channel type formed on the same substrate as the storage cells, the transistors being connected in series with one another and being connected to an adaptive voltage source having a voltage value equal to the average bit line voltage of a selected group of the storage cells; and an amplifier circuit formed on the same substrate as the storage cells and having an input connected to the junction between the transistors and having an output for providing an adaptive bias voltage for the storage cells.
Claim 3
Dependent Claim
23 words
The adaptive bias circuit of claim 1 wherein said series-connected transistors are connected to said supply voltage source used by said storage cells.
Claim 4
Dependent Claim
16 words
The adaptive bias circuit of claim 1 wherein said amplifier circuit is an operational amplifier circuit.
Claim 5
Dependent Claim
94 words
An adaptive bias circuit for producing a bias voltage for storage cells formed on a semiconductor substrate, the bias circuit comprising: first and second field-effect transistors of opposite channel type formed on the same substrate as the storage cells, such transistors being connected in series with one another; and an operational amplifier circuit, having a unity gain factor, being formed on the same substrate as the storage cells, having an input terminal connected to the junction between the transistors, and having an output terminal for providing an adaptive bias voltage for the storage cells.
Claim 6
Dependent Claim
94 words
An adaptive bias circuit for producing a bias voltage for storage cells formed on a semiconductor substrate, the bias circuit comprising: first and second field-effect transistors of opposite channel type formed on the same substrate as the storage cells, such transistors being connected in series with one another; and an operational amplifier circuit, having a unity gain factor, being formed on the same substrate as the storage cells, having an input terminal connected to the junction between the transistors, and having an output terminal for providing an adaptive bias voltage for the storage cells.
Claim 7
Dependent Claim
118 words
An adaptive bias circuit for producing a bias voltage for storage cells formed on a semiconductor substrate, the bias circuit comprising: first and second field-effect transistors of opposite channel type formed on the same substrate as the storage cells, such transistors being connected in series with one another, wherein a gate terminal and a drain terminal of the first transistor are connected together and a gate terminal and a source terminal of the second transistor are connected together; and an amplifier circuit formed on the same substrate as the storage cells and having an input terminal connected to the junction between the transistors and having an output terminal for providing an adaptive bias voltage for the storage cells.
Claim 8
Dependent Claim
118 words
An adaptive bias circuit for producing a bias voltage for storage cells formed on a semiconductor substrate, the bias circuit comprising: first and second field-effect transistors of opposite channel type formed on the same substrate as the storage cells, such transistors being connected in series with one another, wherein a gate terminal and a drain terminal of the first transistor are connected together and a gate terminal and a source terminal of the second transistor are connected together; and an amplifier circuit formed on the same substrate as the storage cells and having an input terminal connected to the junction between the transistors and having an output terminal for providing an adaptive bias voltage for the storage cells.
Claim 9
Dependent Claim
121 words
An adaptive bias circuit for producing a bias voltage for storage cells formed on a semiconductor substrate, the bias circuit comprising: first and second field-effect transistors of opposite channel type formed on the same substrate as the storage cells, such transistors being connected in series with one another; and an amplifier circuit formed on the same substrate as the storage cells and having an input terminal connected to the junction between the transistors and having an output terminal for providing an adaptive bias voltage for the storage cells, wherein a gate terminal of the first transistor is connected to an output terminal of the amplifier circuit and a gate terminal and a source terminal of the second transistor are connected together.
Claim 10
Dependent Claim
121 words
An adaptive bias circuit for producing a bias voltage for storage cells formed on a semiconductor substrate, the bias circuit comprising: first and second field-effect transistors of opposite channel type formed on the same substrate as the storage cells, such transistors being connected in series with one another; and an amplifier circuit formed on the same substrate as the storage cells and having an input terminal connected to the junction between the transistors and having an output terminal for providing an adaptive bias voltage for the storage cells, wherein a gate terminal of the first transistor is connected to an output terminal of the amplifier circuit and a gate terminal and a source terminal of the second transistor are connected together.
Claim 11
Dependent Claim
137 words
An adaptive bias circuit for producing a bias voltage for storage cells formed on a semiconductor substrate, the bias circuit comprising: first and second field-effect transistors of opposite channel type formed on the same substrate as the storage cells, such transistors being connected in series with one another, wherein a drain terminal of the first transistor is connected to a drain terminal of the second transistor, a source terminal of the first transistor is connected to a higher level voltage source and a source terminal of the second transistor is connected to a lower level voltage source; and an amplifier circuit formed on the same substrate as the storage cells and having an input terminal connected to the junction between the transistors and having an output terminal for providing an adaptive bias voltage for the storage cells.
Claim 12
Dependent Claim
137 words
An adaptive bias circuit for producing a bias voltage for storage cells formed on a semiconductor substrate, the bias circuit comprising: first and second field-effect transistors of opposite channel type formed on the same substrate as the storage cells, such transistors being connected in series with one another, wherein a drain terminal of the first transistor is connected to a drain terminal of the second transistor, a source terminal of the first transistor is connected to a higher level voltage source and a source terminal of the second transistor is connected to a lower level voltage source; and an amplifier circuit formed on the same substrate as the storage cells and having an input terminal connected to the junction between the transistors and having an output terminal for providing an adaptive bias voltage for the storage cells.
Claim 13
Dependent Claim
36 words
The adaptive bias circuit of either claim 7 , wherein said gate terminal and a drain terminal of said first transistor and said gate terminal and said source terminal of said second transistor are connected together.
Claim 14
Dependent Claim
42 words
The adaptive bias circuit of either claim 7 , wherein a gate terminal of said first transistor is connected to an output terminal of said amplifier circuit and a gate terminal and a source terminal of said second transistor are connected together.
Claim 15
Dependent Claim
154 words
An adaptive bias circuit for producing a bias voltage for storage cells formed on a semiconductor substrate, the bias circuit comprising: first and second field-effect transistors of opposite channel type formed on the same substrate as the storage cells, such transistors being connected in series with one another, wherein a drain terminal of the first transistor is connected to a drain terminal of the second transistor, a source terminal of the first transistor is connected to an adaptive voltage source having a voltage value equal to an average bit line voltage of a selected group of storage cells and a source terminal of the second transistor is connected to a lower level voltage source; and an amplifier circuit formed on the same substrate as the storage cells and having an input terminal connected to the junction between the transistors and having an output terminal for providing an adaptive bias voltage for the storage cells.
Claim 16
Dependent Claim
154 words
An adaptive bias circuit for producing a bias voltage for storage cells formed on a semiconductor substrate, the bias circuit comprising: first and second field-effect transistors of opposite channel type formed on the same substrate as the storage cells, such transistors being connected in series with one another, wherein a drain terminal of the first transistor is connected to a drain terminal of the second transistor, a source terminal of the first transistor is connected to an adaptive voltage source having a voltage value equal to an average bit line voltage of a selected group of storage cells and a source terminal of the second transistor is connected to a lower level voltage source; and an amplifier circuit formed on the same substrate as the storage cells and having an input terminal connected to the junction between the transistors and having an output terminal for providing an adaptive bias voltage for the storage cells.
Claim 17
Dependent Claim
39 words
The adaptive bias circuit of either claim 10 , wherein a gate terminal and said drain terminal of said first transistor are connected together and a gate terminal and said source terminal of said second transistor are connected together.
Claim 18
Dependent Claim
42 words
The adaptive bias circuit of either claim 10 , wherein a gate terminal of said first transistor is connected to an output terminal of said amplifier circuit and a gate terminal and a source terminal of said second transistor are connected together.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-10-08 | 2005-04-09 | 2005-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-10-08 | 2009-04-09 | 2009-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-10-08 | 2013-04-09 | 2013-10-09 | $7700.00 | Window Closed / Lapsed |