Translinear static memory cell with bipolar and MOS devices

Claim 2

A translinear memory cell, comprising: a first access line; a pair of second access lines each connected to a source of power; a pair of cross-coupled bipolar transistors wherein the base of each transistor is connected to the collector of the other transistor and the emitters of the two transistors are connected in common; and a pair of field-effect transistors each having its gate connected to said first access line, one of its source and drain connected to a respective one of said second access lines and the other of its source and drain connected to the base of a respective one of said bipolar transistors to function as load devices for supplying power from said second access lines to said bipolar transistors and to conduct information between said bipolar transistors and said second access lines.

Claim 3

The memory cell of claim 1 wherein said bipolar transistors are of opposite conductivity type than said field-effect transistors.

Claim 4

The memory cell of claim 2 wherein said bipolar transistors are NPN transistors and said field-effect transistors are p-channel MOSFETS having their sources connected to the respective bit lines and their drains connected to the respective bases.

Claim 5

The memory cell of claim 1 wherein said transistors are embodied in a monolithic integrated circuit and said pair of field-effect transistors are disposed above said pair of bipolar transistors.

Claim 6

The memory cell of claim 4 wherein said field-effect transistors are respectively connected to said bipolar transistors by means of a conducting layer sandwiched between said field-effect transistors and said bipolar transistors.

Claim 7

The memory cell of claim 5 wherein said conducting layer is comprised of a silicided polysilicon.

Claim 8

The memory cell of claim 6 wherein said field-effect transistors are formed in a recrystallized polysilicon layer within said integrated circuit.

Claim 9

A translinear memory circuit, comprising: a matrix of memory cells arranged in a plurality of rows and columns, each cell including a pair of cross-coupled bipolar transistors and a pair of MOS transistors each having one of its source and drain connected to the base of a respective one of said bipolar transistors; a plurality of word lines respectively associated with the rows of memory cells, each word line being connected to the gate terminals of both MOS transistors in each memory cell of an associated row of cells; a pair of bit lines for each column of memory cells, each of the bit lines being connected to the other of the source and drain of a respective one of the MOS transistors in each cell in the column; and means for applying a substantially constant voltage to each of said bit lines so that each of said MOS transistors functions as a load device to supply power to said cells.

Claim 10

A translinear memory circuit, comprising: a matrix of memory cells arranged in a plurality of rows and columns, each cell including a pair of cross-coupled bipolar transistors and a pair of MOS transistors each having one of its source and drain connected to the base of a respective one of said bipolar transistors; a plurality of word lines respectively associated with the rows of memory cells, each word line being connected to the gate terminals of both MOS transistors in each memory cell of an associated row of cells; a pair of bit lines for each column of memory cells, each of the bit lines being connected to the other of the source and drain of a respective one of the MOS transistors in each cell in the column; and means for applying a substantially constant voltage to each of said bit lines so that each of said MOS transistors functions as a load device to supply power to said cells.

Claim 11

The memory circuit of claim 8 further including means for sensing the current in each of said bit lines.

Claim 12

The memory circuit of claim 8 further including means for selectively altering the voltage of one bit line of a pair of bit lines to thereby drain the current from a particular memory cell in a column of cells.

Claim 13

The memory circuit of claim 10 further including means for increasing the conductivity of the MOS transistors in the row of memory cells in which said particular memory cell is located while decreasing the conductivity of the MOS transistors in the other rows during the time that the voltage of said bit line is selectively altered.

Claim 14

The memory circuit of claim 8 wherein said bipolar transistors are NPN transistors each having its base coupled to the collector of the other bipolar transistor in a cell, and said MOS transistors are p-channel devices having their source terminals connected to said bit lines and their drain terminals connected to said bipolar transistors, respectively.

Claim 15

The memory cell of claim 1 including a further access line that is connected to the common emitters of said bipolar transistors, and means for varying the voltage on said further access line.

Claim 16

The memory circuit of claim 8 further including a second plurality of word lines respectively associated with the rows of memory cells, each word line in said second plurality of word lines being connected to the cross-coupled bipolar transistors in each memory cell of an associated row of cells, and means for selectively varying the voltages on said second plurality of word lines.

Claim 17

The memory circuit of claim 14 wherein the two cross-coupled bipolar transistors in each memory cell have emitter terminals that are connected in common and wherein the word lines in said second plurality of word lines are connected to said emitters.

Claim 18

The memory circuit of claim 8 further including a plurality of auxiliary select lines respectively associated with the columns of memory cells, each select line being connected to the cross-coupled bipolar transistors in each memory cell of an associated column of cells, and means for selectively varying the voltages on said auxiliary select lines.

Claim 19

The memory circuit of claim 16 wherein the two cross-coupled bipolar transistors in each memory cell have emitter terminals that are connected in common, and wherein said select lines are connected to said emitters.

Claim 20

A memory cell, comprising: a first access line; a pair of second access lines; a pair of cross-coupled bipolar transistors wherein the base of each transistor is connected to the collector of the other transistor and the emitters of the two transistors are connected in common; and a pair of field-effect transistors of opposite conductivity type than said bipolar transistors, each of said field-effect transistors having its gate connected to said first access line, one of its source and drain connected to a respective one of said second access lines and the other of its source and drain connected to the base of a respective one of said bipolar transistors, said field-effect transistors functioning as both load impedance devices to supply power to said bipolar transistors and coupling devices to couple said bipolar transistors to said second access lines.

Claim 21

A memory cell, comprising: a first access line; a pair of second access lines; a pair of cross-coupled bipolar transistors wherein the base of each transistor is connected to the collector of the other transistor and the emitters of the two transistors are connected in common; and a pair of field-effect transistors of opposite conductivity type than said bipolar transistors, each of said field-effect transistors having its gate connected to said first access line, one of its source and drain connected to a respective one of said second access lines and the other of its source and drain connected to the base of a respective one of said bipolar transistors, said field-effect transistors functioning as both load impedance devices to supply power to said bipolar transistors and coupling devices to couple said bipolar transistors to said second access lines.

Claim 22

The memory cell of claim 18 wherein said bipolar transistors are NPN transistors and said field-effect transistors are p-channel MOSFETS having their sources connected to the respective bit lines and their drains connected to the respective bases.

Claim 23

The memory cell of claim 18 wherein said transistors are embodied in a monolithic integrated circuit and said pair of field-effect transistors are disposed above said pair of bipolar transistors.

Claim 24

The memory cell of claim 20 wherein said field-effect transistors are respective connected to said bipolar transistors by means of a conducting layer sandwiched between said field-effect transistors and said bipolar transistors.

Claim 25

The memory cell of claim 21 wherein said conducting layer is comprised of a silicided polysilicon.

Claim 26

The memory cell of claim 22 wherein said MOS transistors are formed in a recrystallized polysilicon layer within said integrated circuit.

Claim 27

A translinear memory cell embodied in a monolithic integrated circuit, comprising: a first access line; a pair of second access lines; a pair of cross-coupled bipolar transistors wherein the base of each transistor is connected to the collector of the other transistor and the emitters of the two transistors are connected in common; and a pair of field-effect transistors disposed above said pair of bipolar transistors in said monolithic circuit, each of said field-effect transistors having its gate connected to said first access line, one of its source and drain connected to a respective one of said second access lines and the other of its source and drain connected to the base of a respective one of said bipolar transistors, to function as load devices for supplying power from said second access lines to said bipolar transistors and to conduct information between said bipolar transistors and said second access lines.

Claim 28

A translinear memory cell embodied in a monolithic integrated circuit, comprising: a first access line; a pair of second access lines; a pair of cross-coupled bipolar transistors wherein the base of each transistor is connected to the collector of the other transistor and the emitters of the two transistors are connected in common; and a pair of field-effect transistors disposed above said pair of bipolar transistors in said monolithic circuit, each of said field-effect transistors having its gate connected to said first access line, one of its source and drain connected to a respective one of said second access lines and the other of its source and drain connected to the base of a respective one of said bipolar transistors, to function as load devices for supplying power from said second access lines to said bipolar transistors and to conduct information between said bipolar transistors and said second access lines.

Claim 29

The memory cell of claim 24 wherein said field-effect transistors are respectively connected to said bipolar transistors by means of a conducting layer sandwiched between said field-effect transistors and said bipolar transistors.

Claim 30

The memory cell of claim 25 wherein said conducting layer is comprised of a silicided polysilicon.

Claim 31

The memory cell of claim 26 wherein said MOS transistors are formed in a recrystallized polysilicon layer within said integrated circuit.