Semiconductor integrated circuit device operating at high speed with low current consumption

Claim 2

A semiconductor integrated circuit device operating with first and second power supply voltages as operating power supply voltages, comprising: a plurality of memory cells arranged in rows and columns and formed on a substrate region of a first conductivity type; a plurality of word lines arranged in correspondence to the respective rows and having memory cells of corresponding rows connected thereto respectively; row selection means for transmitting a driving voltage larger in absolute value than said first power supply voltage to a word line corresponding to an addressed row out of said rows in accordance with an address signal; and bias application means for applying a bias voltage to said substrate region; said bias application means including means applying a first bias voltage to said substrate region in an active cycle in which said address signal is made valid and a memory cell selecting operation is performed while applying a second bias voltage different in polarity from said first bias voltage with reference to said second power supply voltage in a standby cycle in which said row selection means is held in an inactive state, the absolute value of the difference between said second bias voltage and said first power supply voltage being substantially equal to that of the difference between said driving voltage and said second power supply voltage.

Claim 3

The semiconductor integrated circuit device in accordance with claim 1, wherein the absolute value of the difference between said first bias voltage and said second power supply voltage is substantially equal to that of the difference between said second bias voltage and said second power supply voltage.

Claim 4

The semiconductor integrated circuit device in accordance with claim 1, further including level adjusting means for adjusting the levels of said first and second bias voltages.

Claim 5

The semiconductor integrated circuit device in accordance with claim 1, wherein said bias application means includes: reference voltage generation means for generating a first reference voltage corresponding to said first bias voltage, an output node outputting said first bias voltage, compare means comparing a voltage corresponding to the voltage at said output node with said first reference voltage, and means for supplying charges to said output node to adjust the voltage level of said output node in accordance with an output signal of said compare means.

Claim 6

The semiconductor integrated circuit device in accordance with claim 1, further comprising: a peripheral insulated gate field-effect transistor formed on a second conductivity type substrate region and performing a prescribed function when activated, and second bias application means for applying a third bias voltage to said second conductivity type substrate region in said active cycle while applying a fourth bias voltage in said standby cycle, said third and fourth bias voltages being different in polarity from each other with reference to said first power supply voltage.

Claim 7

The semiconductor integrated circuit device in accordance with claim 5, wherein an arithmetic mean of said third and fourth bias voltages are substantially equal to said first power supply voltage.

Claim 8

The semiconductor integrated circuit device in accordance with claim 5, wherein the ratio of said driving voltage to said first power supply voltage is substantially equal to the ratio of said fourth bias voltage to said first power supply voltage.

Claim 9

A semiconductor integrated circuit device comprising: an internal circuit including an insulated gate field-effect transistor formed on a first conductivity type semiconductor substrate region having a source coupled to receive a first reference voltage, for executing a prescribed function when activated; and bias application means for applying a first bias voltage to the substrate region in activation of said internal circuit while applying a second bias voltage being different in polarity from said first bias voltage with reference to said first reference voltage in inactivation of said internal circuit in accordance with an operating mode instructing signal instructing an active and inactive state of said internal circuit, an arithmetic mean of said first and second bias voltages being substantially equal to said first reference voltage.

Claim 10

A semiconductor integrated circuit device comprising: an internal circuit including an insulated gate field-effect transistor formed on a first conductivity type semiconductor substrate region having a source coupled to receive a first reference voltage, for executing a prescribed function when activated; and bias application means for applying a first bias voltage to the substrate region in activation of said internal circuit while applying a second bias voltage being different in polarity from said first bias voltage with reference to said first reference voltage in inactivation of said internal circuit in accordance with an operating mode instructing signal instructing an active and inactive state of said internal circuit, an arithmetic mean of said first and second bias voltages being substantially equal to said first reference voltage.

Claim 11

The semiconductor integrated circuit device in accordance with claim 8, further including level adjusting means for adjusting the levels of said first and second bias voltages.

Claim 12

The semiconductor integrated circuit device in accordance with claim 8, wherein said bias application means includes: reference voltage generation means for generating a second reference voltage corresponding to said first bias voltage, an output node outputting said first bias voltage, compare means for comparing a voltage corresponding to the voltage at said output node with said second reference voltage, and means for supplying charges to said output node and adjusting the voltage level of said output node in accordance with an output signal of said compare means.

Claim 13

A semiconductor integrated circuit device operating with first and second power supply voltages as operating power supply voltages, comprising: a plurality of memory cells arranged in rows and columns; a plurality of word lines arranged in correspondence to the respective rows and having the memory cells of corresponding rows connected thereto and receiving a driving voltage larger in absolute value than said first power supply voltage when selected; a peripheral circuit including an insulated gate field-effect transistor formed on a first conductivity type substrate region and performing a prescribed operation when activated; and bias application means for applying a bias voltage to the substrate region; said bias application means including means for applying a first bias voltage to said substrate region in activation of said peripheral circuit while applying a second bias voltage being different in polarity from said first bias voltage with reference to said second power supply voltage in inactivation of said peripheral circuit in accordance with an operating mode instructing signal instructing activation and inactivation of said peripheral circuit, the absolute value of the difference between said second bias voltage and said first power supply voltage being substantially equal to that of the difference between said driving voltage and said second power supply voltage.

Claim 14

A semiconductor integrated circuit device operating with first and second power supply voltages as operating power supply voltages, comprising: a plurality of memory cells arranged in rows and columns; a plurality of word lines arranged in correspondence to the respective rows and having the memory cells of corresponding rows connected thereto and receiving a driving voltage larger in absolute value than said first power supply voltage when selected; a peripheral circuit including an insulated gate field-effect transistor formed on a first conductivity type substrate region and performing a prescribed operation when activated; and bias application means for applying a bias voltage to the substrate region; said bias application means including means for applying a first bias voltage to said substrate region in activation of said peripheral circuit while applying a second bias voltage being different in polarity from said first bias voltage with reference to said second power supply voltage in inactivation of said peripheral circuit in accordance with an operating mode instructing signal instructing activation and inactivation of said peripheral circuit, the absolute value of the difference between said second bias voltage and said first power supply voltage being substantially equal to that of the difference between said driving voltage and said second power supply voltage.

Claim 15

The semiconductor integrated circuit device in accordance with claim 11, wherein the absolute value of the difference between said first bias voltage and said second power supply voltage is substantially equal to that of the difference between said second bias voltage and said second power supply voltage.

Claim 16

The semiconductor integrated circuit device in accordance with claim 11, further including level adjusting means for adjusting the levels of said first and second bias voltages.

Claim 17

The semiconductor integrated circuit device in accordance with claim 11, wherein said bias application means includes: reference voltage generation means for generating a first reference voltage corresponding to said first bias voltage, an output node outputting said first bias voltage, compare means for comparing a voltage corresponding to the voltage of said output node with said first reference voltage, and means for supplying charges to said output node and adjusting the voltage level of said output node in accordance with an output signal of said compare means.

Claim 18

The semiconductor integrated circuit device in accordance with claim 11, further comprising: a peripheral insulated gate field-effect transistor formed on a second conductivity type substrate region, included in said peripheral circuit and performing a prescribed function when activated, and second bias application means applying a third bias voltage to said second conductivity type substrate region in an active cycle of said peripheral circuit while applying a fourth bias voltage in a standby cycle of said peripheral circuit, said third and fourth bias voltages being different in polarity from each other with reference to said first power supply voltage.

Claim 19

A semiconductor integrated circuit device operating with first and second power supply voltages as operating power supply voltages, comprising: a plurality of memory cells arranged in rows and columns; a plurality of word lines arranged in correspondence to the respective rows and having the memory cells of corresponding rows connected thereto and receiving a driving voltage larger in absolute value than said first power supply voltage when selected; a peripheral circuit including an insulated gate field-effect transistor formed on a substrate region, for performing a prescribed operation when activated; and bias application means for applying a bias voltage to said substrate region; said bias application means including means for applying a first bias voltage to said substrate region in activation of said peripheral circuit while applying a second bias voltage being different in polarity from said first bias voltage with reference to said first power supply voltage in inactivation of said peripheral circuit in accordance with an operating mode instructing signal instructing activation and inactivation of said peripheral circuit, the absolute value of the difference between said second bias voltage and said second power supply voltage being substantially equal to that of the difference between said driving voltage and said second power supply voltage.

Claim 20

A semiconductor integrated circuit device operating with first and second power supply voltages as operating power supply voltages, comprising: a plurality of memory cells arranged in rows and columns; a plurality of word lines arranged in correspondence to the respective rows and having the memory cells of corresponding rows connected thereto and receiving a driving voltage larger in absolute value than said first power supply voltage when selected; a peripheral circuit including an insulated gate field-effect transistor formed on a substrate region, for performing a prescribed operation when activated; and bias application means for applying a bias voltage to said substrate region; said bias application means including means for applying a first bias voltage to said substrate region in activation of said peripheral circuit while applying a second bias voltage being different in polarity from said first bias voltage with reference to said first power supply voltage in inactivation of said peripheral circuit in accordance with an operating mode instructing signal instructing activation and inactivation of said peripheral circuit, the absolute value of the difference between said second bias voltage and said second power supply voltage being substantially equal to that of the difference between said driving voltage and said second power supply voltage.

Claim 21

The semiconductor integrated circuit device in accordance with claim 16, wherein the absolute value of the difference between said first bias voltage and said second power supply voltage is substantially equal to that of the difference between said second bias voltage and said second power supply voltage.

Claim 22

The semiconductor integrated circuit device in accordance with claim 16, further including level adjusting means for adjusting the levels of said first and second bias voltages.

Claim 23

The semiconductor integrated circuit device in accordance with claim 16, wherein said bias application means includes: reference voltage generation means for generating a first reference voltage corresponding to said first bias voltage, an output node outputting said first bias voltage, compare means for comparing a voltage corresponding to the voltage at said output node with said first reference voltage, and means for supplying charges to said output node and adjusting the voltage level of said output node in accordance with an output signal of said compare means.

Claim 24

The semiconductor integrated circuit device in accordance with claim 16, further comprising: a peripheral insulated gate field-effect transistor formed on a second conductivity type substrate region and performing a prescribed function when activated, and second bias application means applying a third bias voltage to said second conductivity type substrate region in an active cycle of said peripheral circuit while applying a fourth bias voltage in a standby cycle of said peripheral circuit, said third and fourth bias voltages being different in polarity from each other with reference to said first power supply voltage, said peripheral insulated gate field-effect transistor included in said peripheral circuit.