US6404670B2
Expired / Lapsed
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Multiple ports memory-cell structure
Assignee: UNIRAM Tech Inc
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Filing: 2001-01-26
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Granted: 2002-06-11
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Expires: 2021-01-26
Abstract
Abstract A semiconductor memory array comprising a plurality of memory cells wherein each memory cell further includes a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells. The memory array further includes a memory cell read/write voltage control circuit for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V0 and second voltage V1 wherein Vdd>V1>V0>Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array. The memory array further includes a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second wordlines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage. In a preferred embodiment, the memory cell read/write voltage control circuit further includes a wordline voltage control circuit for providing a higher wordline voltage in a write operation and a lower wordline voltage in a read operation. In another preferred embodiment, the memory cell read/write voltage control circuit further includes a memory-core power supply voltage (CVdd) control circuit for providing a higher CVdd voltage in a read operation and a lower CVdd voltage in a write operation. In another preferred embodiment, the memory cell read/write voltage control circuit further includes a memory-core ground voltage (CVss) control circuit for providing a lower CVss voltage in a read operation and a higher CVss voltage in a write operation.
Inventors
- 👤 Jeng-Jye Shau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:30
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/4063; G11C11/407; G11C11/4074; G11C11/409; G11C11/4091; G11C11/4094; G11C11/4096; G11C11/4097; G11C7/1075; G11C7/12; G11C7/18; G11C8/00; G11C8/12; H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/50
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
153 words
A semiconductor memory array comprising a plurality of memory cells wherein each memory cell further comprising: a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells; a memory cell read/write voltage control means for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V 0 and second voltage V 1 wherein Vdd>V 1 >V 0 >Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array; and a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second word-lines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage.
Claim 2
Dependent Claim
153 words
A semiconductor memory array comprising a plurality of memory cells wherein each memory cell further comprising: a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells; a memory cell read/write voltage control means for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V 0 and second voltage V 1 wherein Vdd>V 1 >V 0 >Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array; and a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second word-lines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage.
Claim 3
Dependent Claim
41 words
The semiconductor memory array of claim 1 wherein: the memory cell read/write voltage control means further includes a wordline voltage control means for providing a higher wordline voltage in a write operation and a lower wordline voltage in a read operation.
Claim 4
Dependent Claim
44 words
The semiconductor memory array of claim 1 wherein: the memory cell read/write voltage control means further includes a memory-core power supply voltage (CVdd) control means for providing a higher CVdd voltage in a read operation and a lower CVdd voltage in a write operation.
Claim 5
Dependent Claim
43 words
The semiconductor memory array of claim 1 wherein: the memory cell read/write voltage control means further includes a memory-core ground voltage (CVss) control means for providing a lower CVss voltage in a read operation and a higher CVss voltage in a write operation.
Claim 6
Dependent Claim
78 words
The semiconductor memory array of claim 1 wherein: the memory cell read/write voltage control means further includes a wordline voltage control means for providing a higher wordline voltage in a write operation and a lower wordline voltage in a read operation; and the memory cell read/write voltage control means further includes a memory-core power supply voltage (CVdd) control means for providing a higher CVdd voltage in a read operation and a lower CVdd voltage in a write operation.
Claim 7
Dependent Claim
77 words
The semiconductor memory array of claim 1 wherein: the memory cell read/write voltage control means further includes a wordline voltage control means for providing a higher wordline voltage in a write operation and a lower wordline voltage in a read operation; and the memory cell read/write voltage control means further includes a memory-core ground voltage (CVss) control means for providing a lower CVss voltage in a read operation and a higher CVss voltage in a write operation.
Claim 8
Dependent Claim
125 words
A semiconductor memory array comprising a plurality of memory cells wherein each memory cell further comprising: a bit-line and a word-line connected to each of the memory cells; a memory cell read/write voltage control means for controlling the bit-line to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V 0 and second voltage V 1 wherein Vdd>V 1 >V 0 >Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array; and a read/write port for carrying out a read/write operation by activating the word-line and by controlling the bit-line to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage.
Claim 9
Dependent Claim
125 words
A semiconductor memory array comprising a plurality of memory cells wherein each memory cell further comprising: a bit-line and a word-line connected to each of the memory cells; a memory cell read/write voltage control means for controlling the bit-line to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V 0 and second voltage V 1 wherein Vdd>V 1 >V 0 >Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array; and a read/write port for carrying out a read/write operation by activating the word-line and by controlling the bit-line to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage.
Claim 10
Dependent Claim
41 words
The semiconductor memory array of claim 7 wherein: the memory cell read/write voltage control means further includes a wordline voltage control means for providing a higher wordline voltage in a write operation and a lower wordline voltage in a read operation.
Claim 11
Dependent Claim
44 words
The semiconductor memory array of claim 7 wherein: the memory cell read/write voltage control means further includes a memory-core power supply voltage (CVdd) control means for providing a higher CVdd voltage in a read operation and a lower CVdd voltage in a write operation.
Claim 12
Dependent Claim
43 words
The semiconductor memory array of claim 7 wherein: the memory cell read/write voltage control means further includes a memory-core ground voltage (CVss) control means for providing a lower CVss voltage in a read operation and a higher CVss voltage in a write operation.
Claim 13
Dependent Claim
78 words
The semiconductor memory array of claim 7 wherein: the memory cell read/write voltage control means further includes a wordline voltage control means for providing a higher wordline voltage in a write operation and a lower wordline voltage in a read operation; and the memory cell read/write voltage control means further includes a memory-core power supply voltage (CVdd) control means for providing a higher CVdd voltage in a read operation and a lower CVdd voltage in a write operation.
Claim 14
Dependent Claim
77 words
The semiconductor memory array of claim 7 wherein: the memory cell read/write voltage control means further includes a wordline voltage control means for providing a higher wordline voltage in a write operation and a lower wordline voltage in a read operation; and the memory cell read/write voltage control means further includes a memory-core ground voltage (CVss) control means for providing a lower CVss voltage in a read operation and a higher CVss voltage in a write operation.
Claim 15
Dependent Claim
72 words
A semiconductor memory array comprising a plurality of memory cells wherein each memory cell further comprising: a bit-line and a word-line connected to each of the memory cells; a memory cell read/write voltage control means for controlling the bit-line to have at least three bitline voltage ranges between a power supply voltage and a ground voltage for the memory array provided for carrying out read/write operations through the bit-line and the word-line.
Claim 16
Dependent Claim
72 words
A semiconductor memory array comprising a plurality of memory cells wherein each memory cell further comprising: a bit-line and a word-line connected to each of the memory cells; a memory cell read/write voltage control means for controlling the bit-line to have at least three bitline voltage ranges between a power supply voltage and a ground voltage for the memory array provided for carrying out read/write operations through the bit-line and the word-line.
Claim 17
Dependent Claim
24 words
The semiconductor memory array of claim 13 wherein: each of the memory cells comprising six-transistors constituting a 6T static random access memory (SRAM) cell.
Claim 18
Dependent Claim
43 words
The semiconductor memory array of claim 13 wherein: each of the memory cells comprising five-transistors constituting a 5T static random access memory (SRAM) cell with one of said five transistors functioning as a pass-transistor connected to a single wordline and a single bitline.
Claim 19
Independent Claim
75 words
A method for performing data access to a semiconductor memory array having a plurality of memory cells comprising: connecting a bit-line and a word-line to each of the memory cells; providing a memory cell read/write voltage control means for controlling the bit-line to have at least three bitline voltage ranges between a power supply voltage and a ground voltage for the memory array to carry out said data access through the bit-line and the word-line.
Claim 20
Independent Claim
75 words
A method for performing data access to a semiconductor memory array having a plurality of memory cells comprising: connecting a bit-line and a word-line to each of the memory cells; providing a memory cell read/write voltage control means for controlling the bit-line to have at least three bitline voltage ranges between a power supply voltage and a ground voltage for the memory array to carry out said data access through the bit-line and the word-line.
Claim 21
Dependent Claim
58 words
The method of claim 16 further comprising a step of: configuring each of the memory cells as five-transistors (5T) static random access memory (SRAM) cell with one of said five transistors functioning as a pass-transistor connected to a single wordline and a single bitline for carrying out said data access through said single bitline and said single wordline.
Claim 22
Dependent Claim
72 words
The method of claim 16 further comprising a step of: configuring each of the memory cells as six-transistors (6T) static random access memory (SRAM) cell with two of said five transistors functioning as a pass-transistors connected to a first and second wordlines and a first and second bitlines for carrying out said data access through said first and second bitlines and said first and second wordlines as a dual-port data-access memory array.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-06-10 | 2005-12-10 | 2006-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-10 | 2009-12-10 | 2010-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-10 | 2013-12-10 | 2014-06-11 | $7700.00 | Window Closed / Lapsed |