System for calibrating timing of an integrated circuit wafer tester

Claim 1

A method for calibrating timing of an integrated circuit (IC) tester and an interconnect system for connecting the IC tester to input/output (I/O) terminals of an IC implemented on a semiconductor wafer, wherein the IC tester includes a plurality of tester channels for testing the IC implemented on the semiconductor wafer, wherein the tester also includes a spare channel, wherein the tester includes means for sending a sequence of clock signal edges to the tester channels and to the spare channel, wherein the tester channels and the spare channel each include means for generating an output signal having an edge following receipt of any of said clock signal edges with a drive delay including a programmable drive delay and an adjustable drive calibration delay and for sampling an input signal following any of said clock signal edges with a compare delay including a programmable compare delay and an adjustable compare calibration delay, and wherein the interconnect system contacts said IC to provide a first conductive path between each said I/O terminal and a corresponding one of said tester channels for conveying signals therebetween, the method comprising the steps of: a. adapting said interconnect system to provide a second conductive path; b. providing a plurality of first conductors, each corresponding to a separate one of said tester channels; and c. for each tester channel of said plurality of tester channels: c1. causing said interconnect system to contact the tester channel's corresponding first conductor, wherein the corresponding first conductor and the first and second conductive paths form a first signal path between said tester channel and said spare channel, c2. causing said tester channel to repeatedly send its output signal as an input signal to said spare channel via said first signal path, and c3. concurrent with substep c2, causing said spare channel to sample its input signal with a fixed delay following said clock signal edges.

Claim 2

A method for calibrating timing of an integrated circuit (IC) tester and an interconnect system for connecting the IC tester to input/output (I/O) terminals of an IC implemented on a semiconductor wafer, wherein the IC tester includes a plurality of tester channels for testing the IC implemented on the semiconductor wafer, wherein the tester also includes a spare channel, wherein the tester includes means for sending a sequence of clock signal edges to the tester channels and to the spare channel, wherein the tester channels and the spare channel each include means for generating an output signal having an edge following receipt of any of said clock signal edges with a drive delay including a programmable drive delay and an adjustable drive calibration delay and for sampling an input signal following any of said clock signal edges with a compare delay including a programmable compare delay and an adjustable compare calibration delay, and wherein the interconnect system contacts said IC to provide a first conductive path between each said I/O terminal and a corresponding one of said tester channels for conveying signals therebetween, the method comprising the steps of: a. adapting said interconnect system to provide a second conductive path; b. providing a plurality of first conductors, each corresponding to a separate one of said tester channels; and c. for each tester channel of said plurality of tester channels: c1. causing said interconnect system to contact the tester channel's corresponding first conductor, wherein the corresponding first conductor and the first and second conductive paths form a first signal path between said tester channel and said spare channel, c2. causing said tester channel to repeatedly send its output signal as an input signal to said spare channel via said first signal path, and c3. concurrent with substep c2, causing said spare channel to sample its input signal with a fixed delay following said clock signal edges.

Claim 10

A method for calibrating timing of an integrated circuit (IC) tester and an interconnect system, wherein the IC tester has a plurality of tester channels for testing an IC implemented on a semiconductor wafer, wherein the wafer has a plurality of input/output (I/O) terminals, each I/O terminal corresponding to a separate one of said tester channels, wherein the tester includes means for sending a sequence of clock signal edges to the tester channels and to the spare channel, wherein the tester channels and the spare channel each include means for generating an output signal having an edge following receipt of any of said clock signal edges with a drive delay including a programmable drive delay and an adjustable drive calibration delay and for sampling an input signal following any of said clock signal edges with a compare delay including a programmable compare delay and an adjustable compare calibration delay, and wherein the interconnect system contacts said IC to provide a first conductive path between each said I/O terminal and its corresponding tester channel for conveying signals therebetween, the method comprising the steps of: a. providing a measurement circuit for measuring a time interval between an edge of the clock signal and an edge of an output signal of any one of said tester channels, b. adapting said interconnect system to provide a second conductive path; c. providing a plurality of first conductors, each corresponding to each of said tester channels; and d. for each tester channel of said plurality of tester channels: d1. causing said interconnect system to contact the tester channel's corresponding first conductor, wherein the corresponding first conductor and the first and second conductive paths from a first signal path between said tester channel and said measurement circuit, d2. causing said tester channel to produce output signal edges following said clock signal edges, wherein the first signal path conveys said output signal edges as input signal edges to said measurement circuit, and d3. causing said measurement unit to measure intervals between said clock signal edges and its input signal edges arriving by said first signal path.

Claim 11

A method for calibrating timing of an integrated circuit (IC) tester and an interconnect system, wherein the IC tester has a plurality of tester channels for testing an IC implemented on a semiconductor wafer, wherein the wafer has a plurality of input/output (I/O) terminals, each I/O terminal corresponding to a separate one of said tester channels, wherein the tester includes means for sending a sequence of clock signal edges to the tester channels and to the spare channel, wherein the tester channels and the spare channel each include means for generating an output signal having an edge following receipt of any of said clock signal edges with a drive delay including a programmable drive delay and an adjustable drive calibration delay and for sampling an input signal following any of said clock signal edges with a compare delay including a programmable compare delay and an adjustable compare calibration delay, and wherein the interconnect system contacts said IC to provide a first conductive path between each said I/O terminal and its corresponding tester channel for conveying signals therebetween, the method comprising the steps of: a. providing a measurement circuit for measuring a time interval between an edge of the clock signal and an edge of an output signal of any one of said tester channels, b. adapting said interconnect system to provide a second conductive path; c. providing a plurality of first conductors, each corresponding to each of said tester channels; and d. for each tester channel of said plurality of tester channels: d1. causing said interconnect system to contact the tester channel's corresponding first conductor, wherein the corresponding first conductor and the first and second conductive paths from a first signal path between said tester channel and said measurement circuit, d2. causing said tester channel to produce output signal edges following said clock signal edges, wherein the first signal path conveys said output signal edges as input signal edges to said measurement circuit, and d3. causing said measurement unit to measure intervals between said clock signal edges and its input signal edges arriving by said first signal path.