Patent US6615402B2 successfully refreshed from Google Patents.
US6615402B2
Expired / Lapsed
US
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Interchangeable FPGA-gate array
Assignee: Toshiba Corp
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Filing: 2001-03-27
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Granted: 2003-09-02
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Expires: 2021-03-27
Abstract
Abstract A test facilitating circuit is contained in a FPGA-GATE ARRAY. In the gate array chip there are disposed I/O cells, a boundary scan circuit, a controller and an internal circuit. The arrangement of the external terminals of a package is the same as the arrangement of the external terminals of the FPGA. The test terminal corresponds to the data program terminal of the FPGA. When the FPGA is displaced with a gate array, the data program terminal of the FPGA becomes unnecessary and is used as a control terminal for the boundary scan circuit. The position of the test terminal is fixed, thereby to achieve a facilitated, automated and standardized design.
Inventors
- 👤 Yoshio Kaneko
- 👤 Atsushi Tomishima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:04
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; G01R31/318519; G01R31/31701
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
111 words
An interchangeable FPGA-GATE ARRAY comprising: first external terminals disposed at positions corresponding to positions of second external terminals of a FPGA; and a gate array chip having a test circuit; wherein a position of a terminal for controlling said test circuit among said first external terminals corresponds to a position of a data program terminal of said FPGA among said second external terminals, and wherein, when a special buffer of which characteristics are strictly specified and of which functions cannot be changed by a program is provided in said FPGA, a buffer having substantially the same characteristics as the characteristics of said special buffer is provided also in said gate array.
Claim 2
Dependent Claim
111 words
An interchangeable FPGA-GATE ARRAY comprising: first external terminals disposed at positions corresponding to positions of second external terminals of a FPGA; and a gate array chip having a test circuit; wherein a position of a terminal for controlling said test circuit among said first external terminals corresponds to a position of a data program terminal of said FPGA among said second external terminals, and wherein, when a special buffer of which characteristics are strictly specified and of which functions cannot be changed by a program is provided in said FPGA, a buffer having substantially the same characteristics as the characteristics of said special buffer is provided also in said gate array.
Claim 3
Dependent Claim
53 words
The interchangeable FPGA-GATE ARRAY according to claim 1 , wherein a function of a third external terminal other than the data program terminal of said FPGA among said second external terminals is the same as a function of a fourth external terminal corresponding to said third external terminal among said first external terminals.
Claim 4
Dependent Claim
18 words
The interchangeable FPGA-GATE ARRAY according to claim 1 , wherein said test circuit includes a boundary scan circuit.
Claim 5
Dependent Claim
108 words
A manufacturing method of an interchangeable FPGA-GATE ARRAY when developing a system by using a FPGA and mass-producing said system by using a gate array, comprising steps of: forming a logic LSI in a FPGA chip by using a data program terminal of a package of said FPGA; forming said logic LSI and a test circuit in the gate array chip by using a wiring mask; containing said gate array chip in which said logic LSI and said test circuit are formed in the package of said FPGA; using said data program terminal of the package of said FPGA as a test terminal for controlling said test circuit.
Claim 6
Dependent Claim
108 words
A manufacturing method of an interchangeable FPGA-GATE ARRAY when developing a system by using a FPGA and mass-producing said system by using a gate array, comprising steps of: forming a logic LSI in a FPGA chip by using a data program terminal of a package of said FPGA; forming said logic LSI and a test circuit in the gate array chip by using a wiring mask; containing said gate array chip in which said logic LSI and said test circuit are formed in the package of said FPGA; using said data program terminal of the package of said FPGA as a test terminal for controlling said test circuit.
Claim 7
Dependent Claim
55 words
The manufacturing method according to claim 4 , wherein, at the time of having finished the development of said system by using said FPGA, also a print circuit board equipped with said interchangeable FPGA-GATE ARRAY has been already developed, and subsequently, said logic LSI and said test circuit are formed in said gate array chip.
Claim 8
Dependent Claim
73 words
The manufacturing method according to claim 4 , wherein, when a special buffer of which characteristics are strictly specified and of which functions cannot be changed by means of a program is provided in said FPGA, a wafer before a wiring process including the same buffer as said special buffer is prepared in advance, and logic LSI is realized by forming said special buffer in said wafer by means of said wiring process.
Claim 9
Dependent Claim
17 words
The manufacturing method according to claim 4 , wherein said test circuit includes a boundary scan circuit.
Claim 10
Dependent Claim
35 words
The manufacturing method according to claim 4 , wherein data are written into a memory in the FPGA chip by using said data program terminal and a logic LSI is formed in said FPGA chip.
Claim 11
Dependent Claim
24 words
The manufacturing method according to claim 8 , wherein said data are written into said memory by using a controller in said FPGA chip.
Claim 12
Dependent Claim
19 words
The manufacturing method according to claim 9 , wherein said controller is disposed also in said gate array chip.
Claim 13
Dependent Claim
18 words
The manufacturing method according to claim 10 , wherein said controller is used to control said test circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-09-01 | 2007-03-03 | 2007-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-09-01 | 2011-03-03 | 2011-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-09-01 | 2015-03-03 | 2015-09-02 | $7700.00 | Window Closed / Lapsed |