Patent US6611063B1 successfully refreshed from Google Patents.
US6611063B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Resin-encapsulated semiconductor device
Assignee: Renesas Electronics Corp
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Filing: 2000-09-18
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Granted: 2003-08-26
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Expires: 2020-09-18
Abstract
Abstract A method for forming a mold-encapsulated semiconductor device includes the steps of mounting a semiconductor chip on a metallic plate having a metallic interconnect pattern thereon, encapsulating the semiconductor chip on the metallic interconnect pattern, removing the bottom of the metallic plate by etching to expose the metallic interconnect pattern, and forming external terminals on the bottom of the metallic interconnect pattern. The method reduces the thickness as well as the planar dimensions of the semiconductor device.
Inventors
- 👤 Michihiko Ichinose
- 👤 Tomoko Takizawa
- 👤 Hirokazu Honda
- 👤 Keiichirou Kata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 02:25
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/01; H10W70/04; H10W70/042; H10W74/00; H10W74/01; H10W70/40; H10W70/411; H10W70/415; H10W74/012; H10W74/019; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W74/15; H10W90/00; H10W90/701; H10W90/811; H10P; H10P72/00; H10P72/70; H10P72/74; H10P72/7438; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/656; H10W70/67; H10W70/68; H10W70/681; H10W72/00; H10W72/01; H10W72/0198; H10W72/071; H10W72/073; H10W72/075; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/853; H10W72/856; H10W72/874; H10W72/884; H10W72/90; H10W72/941; H10W72/9415; H10W74/131; H10W74/142; H10W90/721; H10W90/724; H10W90/731; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
134 words
A semiconductor device comprising: a semiconductor chip having a plurality of chip electrodes thereon; a metallic interconnect pattern having a top surface connected to said plural chip electrodes and supporting said semiconductor chip, at least a top portion of said metallic interconnect pattern being formed by an electrolytic plating technique; an insulating film covering a bottom surface of said metallic interconnect pattern and having through-holes therein; a plurality of external terminals formed on said bottom surface of said interconnect pattern in said through-holes; a mold resin encapsulating said semiconductor chip on said top surface of said metallic interconnect pattern and said insulating film; another semiconductor chip mounted on said bottom surface of said metallic interconnect pattern; and another mold resin encapsulating said another semiconductor chip on said bottom surface of said metallic interconnect pattern.
Claim 2
Dependent Claim
134 words
A semiconductor device comprising: a semiconductor chip having a plurality of chip electrodes thereon; a metallic interconnect pattern having a top surface connected to said plural chip electrodes and supporting said semiconductor chip, at least a top portion of said metallic interconnect pattern being formed by an electrolytic plating technique; an insulating film covering a bottom surface of said metallic interconnect pattern and having through-holes therein; a plurality of external terminals formed on said bottom surface of said interconnect pattern in said through-holes; a mold resin encapsulating said semiconductor chip on said top surface of said metallic interconnect pattern and said insulating film; another semiconductor chip mounted on said bottom surface of said metallic interconnect pattern; and another mold resin encapsulating said another semiconductor chip on said bottom surface of said metallic interconnect pattern.
References Cited (Backward Citations)
JPH02151496A
Cited
JPH02240940A
Cited
EP0582052A1
Cited
US5592025A
Cited
WO1995026047A1
Cited
US5837567A
Cited
US5905303A
Cited
US6025650A
Cited
US5726489A
Cited
US5990546A
Cited
US5793106A
Cited
US5729432A
Cited
US5874784A
Cited
US5847455A
Cited
JPH09283925A
Cited
JPH10116935A
Cited
US5990545A
Cited
JPH10284544A
Cited
KR19990037053A
Cited
JPH11195733A
Cited
US6204564B1
Cited
US6340606B1
Cited
US6330166B1
Cited
US6316838B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-08-25 | 2007-02-24 | 2007-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-08-25 | 2011-02-24 | 2011-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-08-25 | 2015-02-24 | 2015-08-26 | $7700.00 | Window Closed / Lapsed |