Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers

Claim 2

A delay-locked loop, comprising: a variable delay line configured to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal; a mode delay line configured to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a mode delay relative to the delayed clock signal and the mode delay being a function of the output drive strength signal; a feedback delay line coupled to the mode delay line and operable to generate a feedback clock signal responsive to the mode delayed clock signal, the feedback clock signal having a model delay relative to the mode delayed clock signal; and a comparison circuit configured to receive the input clock signal and coupled to the feedback delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the input and feedback clock signals.

Claim 3

The delay-locked loop of claim 1 wherein the output drive strength signal corresponds to an output drive strength bit stored in a load mode register.

Claim 4

The delay-locked loop of claim 1 wherein the mode delay line generates a mode delayed clock signal having a first mode delay relative to the delayed clock signal responsive to the output drive strength signal having a first logic state and having a second mode delay responsive to the output drive strength signal having a second logic state.

Claim 5

The delay-locked loop of claim 3 wherein the first logic state of the output drive strength signal corresponds to a full-drive mode of operation of an output buffer configured to receive the delayed clock signal, and the second logic state of the output drive strength signal corresponds to a reduced-drive mode of operation of the output buffer.

Claim 6

The delay-locked loop of claim 4 wherein the output buffer has a first output delay when operating in the full-drive mode and a second output delay when operating in the reduced-drive mode, the mode delay line being operable in the reduced-drive mode to provide the second mode delay having a value equal to the magnitude of the first output delay minus the second output delay.

Claim 7

The delay-locked loop of claim 1 wherein the first mode delay comprises a value that is substantially less than a value of the second mode delay.

Claim 8

The delay-locked loop of claim 1 wherein the comparison circuit comprises a phase detection circuit coupled to receive the feedback clock signal and the input clock signal and operable to develop the delay control signal responsive to the relative phases of the feedback and input clock signals.

Claim 9

A delay-locked loop, comprising: a variable delay line configured to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal; a comparison circuit coupled to the variable delay line and configured to receive the input clock signal, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and input clock signals; and a mode delay line configured to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a mode delay relative to the delayed clock signal and the mode delay being a function of the output drive strength signal.

Claim 10

A delay-locked loop, comprising: a variable delay line configured to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal; a comparison circuit coupled to the variable delay line and configured to receive the input clock signal, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and input clock signals; and a mode delay line configured to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a mode delay relative to the delayed clock signal and the mode delay being a function of the output drive strength signal.

Claim 11

The delay-locked loop of claim 8 wherein the first mode delay comprises a value that is substantially less than a value of the second mode delay.

Claim 12

The delay-locked loop of claim 8 wherein the mode delay line generates a mode delayed clock signal having a first mode delay relative to the delayed clock signal responsive to the output drive strength signal having a first logic state and having a second mode delay responsive to the output drive strength signal having a second logic state.

Claim 13

The delay-locked loop of claim 10 wherein the first logic state of the output drive strength signal corresponds to a full-drive mode of operation of an output buffer configured to receive the mode delayed clock signal, and the second logic state of the output drive strength signal corresponds to a reduced-drive mode of operation of the output buffer.

Claim 14

The delay-locked loop of claim 11 wherein the output buffer has a first output delay when operating in the full-drive mode and a second output delay when operating in the reduced-drive mode, the mode delay line being operable in the reduced-drive mode to provide the second mode delay having a value equal to the magnitude of the first output delay minus the second output delay.

Claim 15

The delay-locked loop of claim 8 wherein the output drive strength signal corresponds to a output drive strength bit stored in a load mode register.

Claim 16

The delay-locked loop of claim 8 wherein the comparison circuit comprises: a fixed delay line that generates a feedback clock signal in response to the delayed clock signal, the feedback clock signal having a model delay relative to the delayed clock signal; and a phase detection circuit coupled to receive the feedback clock signal and the input clock signal and operable to develop the delay control signal responsive to the relative phases of the feedback and input clock signals.

Claim 17

A delay-locked loop, comprising: an input buffer configured to receive an input clock signal and operable to generate a buffered clock signal responsive to the input clock signal; a variable delay line coupled to the input buffer and operable to generate a delayed clock signal responsive to the buffered clock signal, the delayed clock signal having a delay relative to the buffered clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal; a mode delay line adapted to receive a output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a first mode delay relative to the delayed clock signal responsive to the output drive strength signal having a first logic state and having a second mode delay responsive to the output drive strength signal having a second logic state; a feedback delay line coupled to the mode delay line and operable to generate a feedback clock signal responsive to the mode delayed clock signal, the feedback clock signal having a model delay relative to the mode delayed clock signal; a comparison circuit coupled to the input buffer and coupled to the feedback delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the buffered and feedback clock signals; and an output buffer coupled to the variable delay line and operable in a full-drive mode responsive to the output drive strength signal having the first logic state to generate a first synchronized output signal in response to the delayed clock signal, and operable in a reduced-drive mode responsive to the output drive strength signal having the second logic state to generate a second synchronized output signal in response to the delayed clock signal.

Claim 18

A delay-locked loop, comprising: an input buffer configured to receive an input clock signal and operable to generate a buffered clock signal responsive to the input clock signal; a variable delay line coupled to the input buffer and operable to generate a delayed clock signal responsive to the buffered clock signal, the delayed clock signal having a delay relative to the buffered clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal; a mode delay line adapted to receive a output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a first mode delay relative to the delayed clock signal responsive to the output drive strength signal having a first logic state and having a second mode delay responsive to the output drive strength signal having a second logic state; a feedback delay line coupled to the mode delay line and operable to generate a feedback clock signal responsive to the mode delayed clock signal, the feedback clock signal having a model delay relative to the mode delayed clock signal; a comparison circuit coupled to the input buffer and coupled to the feedback delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the buffered and feedback clock signals; and an output buffer coupled to the variable delay line and operable in a full-drive mode responsive to the output drive strength signal having the first logic state to generate a first synchronized output signal in response to the delayed clock signal, and operable in a reduced-drive mode responsive to the output drive strength signal having the second logic state to generate a second synchronized output signal in response to the delayed clock signal.

Claim 19

The delay-locked loop of claim 15 wherein the output drive strength signal corresponds to a output drive strength bit stored in a load mode register.

Claim 20

The delay-locked loop of claim 15 wherein the output buffer has a first output delay when operating in the full-drive mode and a second output delay when operating in the reduced-drive mode, the mode delay line being operable in the reduced-drive mode to provide the second mode delay having a value equal to the magnitude of the first output delay minus the second output delay.

Claim 21

The delay-locked loop of claim 15 wherein the first mode delay comprises a value that is substantially less than a value of the second mode delay.

Claim 22

The delay-locked loop of claim 1 wherein the comparison circuit comprises a phase detection circuit coupled to receive the feedback clock signal and the input clock signal and operable to develop the delay control signal responsive to the relative phases of the feedback and input clock signals.

Claim 23

The delay-locked loop of claim 15 wherein the first and second synchronized output signals correspond to first and second synchronized clock signals having voltage and current characteristics associated with the full- and reduced-drive modes of operation, respectively.

Claim 24

A delay-locked loop, comprising: an input buffer configured to receive an input clock signal and operable to generate a buffered clock signal responsive to the input clock signal; a variable delay line coupled to the input buffer and operable to generate a delayed clock signal responsive to the buffered clock signal, the delayed clock signal having a delay relative to the buffered clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal; a comparison circuit coupled to the variable delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and buffered clock signals; a mode delay line configured to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a first mode delay relative to the delayed clock signal responsive to the output drive strength signal having a first logic state and having a second mode delay responsive to the output drive strength signal having a second logic state; and an output buffer coupled to the variable delay line and operable in a full-drive mode responsive to the output drive strength signal having the first logic state to generate a first synchronized output signal in response to the delayed clock signal, and operable in a reduced-drive mode responsive to the output drive strength signal having the second logic state to generate a second synchronized output signal in response to the delayed clock signal.

Claim 25

A delay-locked loop, comprising: an input buffer configured to receive an input clock signal and operable to generate a buffered clock signal responsive to the input clock signal; a variable delay line coupled to the input buffer and operable to generate a delayed clock signal responsive to the buffered clock signal, the delayed clock signal having a delay relative to the buffered clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal; a comparison circuit coupled to the variable delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and buffered clock signals; a mode delay line configured to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a first mode delay relative to the delayed clock signal responsive to the output drive strength signal having a first logic state and having a second mode delay responsive to the output drive strength signal having a second logic state; and an output buffer coupled to the variable delay line and operable in a full-drive mode responsive to the output drive strength signal having the first logic state to generate a first synchronized output signal in response to the delayed clock signal, and operable in a reduced-drive mode responsive to the output drive strength signal having the second logic state to generate a second synchronized output signal in response to the delayed clock signal.

Claim 26

The delay-locked loop of claim 21 wherein the output drive strength signal corresponds to a output drive strength bit stored in a load mode register.

Claim 27

The delay-locked loop of claim 21 wherein the first mode delay comprises a value that is substantially less than a value of the second mode delay.

Claim 28

The delay-locked loop of claim 21 wherein the output buffer has a first output delay when operating in the full-drive mode and a second output delay when operating in the reduced-drive mode, the mode delay line being operable in the reduced-drive mode to provide the second mode delay having a value equal to the magnitude of the first output delay minus the second output delay.

Claim 29

The delay-locked loop of claim 21 wherein the first and second synchronized output signals correspond to first and second synchronized clock signals having voltage and current characteristics associated with the full- and reduced-drive modes of operation, respectively.

Claim 30

The delay-locked loop of claim 21 wherein the comparison circuit comprises: a fixed delay line that generates a feedback clock signal in response to the delayed clock signal, the feedback clock signal having a model delay relative to the delayed clock signal; and a phase detection circuit coupled to receive the feedback clock signal and the input clock signal and operable to develop the delay control signal responsive to the relative phases of the feedback and input clock signals.

Claim 31

A computer system, comprising: a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device coupled to the processor, the memory device comprising, an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a delay-locked loop coupled to at least the read/write circuit and being adapted to receive an input clock signal, the delay-locked loop comprising, a variable delay line configured to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal; a comparison circuit coupled to the variable delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and input clock signals; and a mode delay line adapted to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a mode delay relative to the delayed clock signal and the mode delay being a function of the output drive strength signal.

Claim 32

A computer system, comprising: a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device coupled to the processor, the memory device comprising, an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a delay-locked loop coupled to at least the read/write circuit and being adapted to receive an input clock signal, the delay-locked loop comprising, a variable delay line configured to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal; a comparison circuit coupled to the variable delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and input clock signals; and a mode delay line adapted to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a mode delay relative to the delayed clock signal and the mode delay being a function of the output drive strength signal.

Claim 33

The memory device of claim 27 wherein the memory device comprises a DDR SDRAM and the delayed clock signal is applied to clock an output driver contained in the read/write circuit.

Claim 36

The method of claim 29 wherein the output drive strength bit has two states corresponding to a full-drive and reduced-drive modes of the data signals.

Claim 37

The method of claim 29 wherein generating the delayed clock signal comprises clocking data signals in response to the delayed clock signal.

Claim 40

The method of claim 29 wherein the output drive strength bit has two states corresponding to a full-drive and reduced-drive modes of the data signals.

Claim 41

The method of claim 29 wherein generating the synchronized clock signal comprises clocking data signals in response to the delayed clock signal.