Patent US6596589B2 successfully refreshed from Google Patents.
US6596589B2
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Method of manufacturing a high coupling ratio stacked gate flash memory with an HSG-SI layer
Assignee: Vanguard International Semiconductor Corp
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Filing: 2001-10-12
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Granted: 2003-07-22
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Expires: 2021-10-12
Abstract
Abstract A stacked-gate flash memory cell includes a trench formed in a substrate and a tunneling oxide layer formed on the substrate. A first part of the floating gate is formed on the tunneling oxide layer. A protruding isolation filler is formed in the trench and protrudes over the upper surface of the first part of the floating gate, thereby forming a cavity between the two adjacent raised isolation structures. A second part of the floating gate is formed of HSG-Si over the surface of the cavity to have a U-shaped structure in cross sectional view. A dielectric layer is conformably formed on the surface of the second part of the floating gate and the isolation structures, and a control gate is formed on the dielectric layer.
Inventors
- 👤 Horng-Huei Tseng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:43
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10B; H10B41/00; H10B41/30; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/6891
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
158 words
A method of manufacturing a stacked-gate flash memory, comprising: forming a first dielectric layer on a semiconductor substrate as a tunneling dielectric; forming a first conductive layer on said first dielectric layer; forming a sacrificial layer on said conductive layer; patterning said sacrificial layer, said first dielectric layer, said first conductive layer and said substrate to form trenches in said substrate; forming isolation structures in said trenches; removing said sacrificial layer, thereby forming a cavity between said isolation structures with said isolation structures protruding over said first conductive layer; forming an HSG-Si layer over a surface of said cavity and said isolation structures; removing a portion of said HSG-Si layer to a surface of said isolation structures, wherein said HSG-Si layer and said first conductive layer act as a floating gate; forming a second dielectric layer on a surface of said floating gate; and forming a second conductive layer on said second dielectric layer as a control gate.
Claim 2
Independent Claim
158 words
A method of manufacturing a stacked-gate flash memory, comprising: forming a first dielectric layer on a semiconductor substrate as a tunneling dielectric; forming a first conductive layer on said first dielectric layer; forming a sacrificial layer on said conductive layer; patterning said sacrificial layer, said first dielectric layer, said first conductive layer and said substrate to form trenches in said substrate; forming isolation structures in said trenches; removing said sacrificial layer, thereby forming a cavity between said isolation structures with said isolation structures protruding over said first conductive layer; forming an HSG-Si layer over a surface of said cavity and said isolation structures; removing a portion of said HSG-Si layer to a surface of said isolation structures, wherein said HSG-Si layer and said first conductive layer act as a floating gate; forming a second dielectric layer on a surface of said floating gate; and forming a second conductive layer on said second dielectric layer as a control gate.
Claim 3
Dependent Claim
12 words
The method of claim 1 , wherein said sacrificial layer comprises nitride.
Claim 4
Dependent Claim
17 words
The method of claim 2 , wherein said sacrificial layer is removed by hot phosphorous acid solution.
Claim 5
Dependent Claim
15 words
The method of claim 1 , wherein said HSG-Si layer is removed by chemical-mechanical polishing.
Claim 6
Dependent Claim
13 words
The method of claim 1 , wherein said second dielectric layer comprises oxide/nitride.
Claim 7
Dependent Claim
13 words
The method of claim 1 , wherein said second dielectric layer comprises oxide/nitride/oxide.
Claim 8
Dependent Claim
26 words
The method of claim 1 , further comprising a step of removing an upper portion of the isolation structures prior to forming said second dielectric layer.
Claim 9
Independent Claim
140 words
A method of manufacturing a stacked-gate flash memory, comprising: forming a first dielectric layer on a semiconductor substrate as a tunneling dielectric; forming a sacrificial layer on said first dielectric layer; patterning said sacrificial layer, said first dielectric layer and said substrate to form trenches in said substrate; forming isolation structures in said trenches; removing said sacrificial layer, thereby forming a cavity between said isolation structures with said isolation structures protruding over said first dielectric layer; forming an HSG-Si layer over a surface of said cavity and said isolation structures; removing a portion of said HSG-Si layer to a surface of said isolation structures, wherein said HSG-Si layer acts as a floating gate; forming a second dielectric layer on a surface of said floating gate; and forming a first conductive layer on said second dielectric layer as a control gate.
Claim 10
Independent Claim
140 words
A method of manufacturing a stacked-gate flash memory, comprising: forming a first dielectric layer on a semiconductor substrate as a tunneling dielectric; forming a sacrificial layer on said first dielectric layer; patterning said sacrificial layer, said first dielectric layer and said substrate to form trenches in said substrate; forming isolation structures in said trenches; removing said sacrificial layer, thereby forming a cavity between said isolation structures with said isolation structures protruding over said first dielectric layer; forming an HSG-Si layer over a surface of said cavity and said isolation structures; removing a portion of said HSG-Si layer to a surface of said isolation structures, wherein said HSG-Si layer acts as a floating gate; forming a second dielectric layer on a surface of said floating gate; and forming a first conductive layer on said second dielectric layer as a control gate.
Claim 11
Dependent Claim
26 words
The method of claim 8 , further comprising a step of removing an upper portion of the isolation structures prior to form said second dielectric layer.
Claim 12
Dependent Claim
22 words
The method of claim 8 , further comprising a step of forming a second conductive layer after forming said first dielectric layer.
Claim 13
Dependent Claim
12 words
The method of claim 8 , wherein said sacrificial layer comprises nitride.
Claim 14
Dependent Claim
17 words
The method of claim 11 , wherein said sacrificial layer is removed by hot phosphorous acid solution.
Claim 15
Dependent Claim
15 words
The method of claim 8 , wherein said HSG-Si layer is removed by chemical-mechanical polishing.
Claim 16
Dependent Claim
15 words
The method of claim 8 , wherein said second dielectric layer comprises oxide/nitride or oxide/nitride/oxide.
References Cited (Backward Citations)
US6413809B2
Cited
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