US6593634B2
Expired / Lapsed
US
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Semiconductor device and method of manufacturing the same
Assignee: Seiko Epson Corp
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Filing: 2001-04-12
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Granted: 2003-07-15
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Expires: 2021-04-12
Abstract
Abstract A semiconductor device includes an NMOSFET and a PMOSFET. Each MOSFET includes first and second impurity diffusion layers for forming a source region and a drain region which are formed in a silicon layer of an SOI substrate or the like, a channel region formed between the first and second impurity diffusion layers, a gate insulation layer at least formed on the channel region, and a gate electrode formed on the gate insulation layer. The gate electrode includes a tantalum nitride layer in a region in contact with at least the gate insulation layer. The semiconductor device exhibits high current drive capability and can be manufactured at high yield.
Inventors
- 👤 Tadahiro Ohmi
- 👤 Hiroyuki Shimada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:48
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
112 words
A semiconductor device comprising: first and second impurity diffusion layers forming a source region and a drain region which are formed in a semiconductor layer; a channel region formed between the first and second impurity diffusion layers; a gate insulation layer formed at least on the channel region; and a gate electrode formed on the gate insulation layer, wherein the gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulation layer and a body-centered cubic tantalum layer heteroepitaxially formed over the tantalum nitride layer, wherein a nitrogen/tantalum ratio (x) as shown by TaN x in the tantalum nitride layer is 0.25 to 1.0.
Claim 2
Dependent Claim
112 words
A semiconductor device comprising: first and second impurity diffusion layers forming a source region and a drain region which are formed in a semiconductor layer; a channel region formed between the first and second impurity diffusion layers; a gate insulation layer formed at least on the channel region; and a gate electrode formed on the gate insulation layer, wherein the gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulation layer and a body-centered cubic tantalum layer heteroepitaxially formed over the tantalum nitride layer, wherein a nitrogen/tantalum ratio (x) as shown by TaN x in the tantalum nitride layer is 0.25 to 1.0.
Claim 3
Dependent Claim
25 words
The semiconductor device according to claim 1 , wherein the nitrogen/tantalum ratio (x) shown by TaN x in the tantalum nitride layer is approximately 0.5.
Claim 4
Dependent Claim
22 words
The semiconductor device according to claim 1 , wherein the tantalum nitride layer has a thickness of 1 nm to 300 nm.
Claim 5
Dependent Claim
22 words
The semiconductor device according to claim 1 , wherein the gate electrode further comprises a cap layer formed on the uppermost layer.
Claim 6
Dependent Claim
44 words
The semiconductor device according to claim 4 , wherein the cap layer is formed of at least one material selected from TaN x , TaSi x N y , TiN x , TiAl x N y , Si, and silicide of a transition metal.
Claim 7
Dependent Claim
19 words
The semiconductor device according to claim 5 , wherein the cap layer is formed of the tantalum nitride layer.
Claim 8
Dependent Claim
23 words
The semiconductor device according to claim 1 , wherein suicide layers are formed on part of the first and second impurity diffusion layers.
Claim 9
Dependent Claim
26 words
The semiconductor device according to claim 1 , wherein the semiconductor layer has a silicon on insulator (SOI) structure or a silicon on nothing (SON) structure.
Claim 10
Dependent Claim
147 words
A complementary semiconductor device comprising an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, wherein each of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor comprises: first and second impurity diffusion layers forming a source region and a drain region which are formed in a semiconductor layer; a channel region formed between the first and second impurity diffusion layers; a gate insulation layer formed on the channel region; and a gate electrode formed on the gate insulation layer, wherein the gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulation layer and a body-centered cubic tantalum layer heteroepitaxially formed over the tantalum nitride layer, wherein a nitrogen / tantalum ratio (x) as shown by TaN x in the tantalum nitride layer is 0.25 to 1.0.
Claim 11
Dependent Claim
147 words
A complementary semiconductor device comprising an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, wherein each of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor comprises: first and second impurity diffusion layers forming a source region and a drain region which are formed in a semiconductor layer; a channel region formed between the first and second impurity diffusion layers; a gate insulation layer formed on the channel region; and a gate electrode formed on the gate insulation layer, wherein the gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulation layer and a body-centered cubic tantalum layer heteroepitaxially formed over the tantalum nitride layer, wherein a nitrogen / tantalum ratio (x) as shown by TaN x in the tantalum nitride layer is 0.25 to 1.0.
Claim 12
Dependent Claim
26 words
The complementary semiconductor device according to claim 9 , wherein the nitrogen/tantalum ratio (x) shown by TaN x in the tantalum nitride layer is approximately 0.5.
Claim 13
Dependent Claim
23 words
The complementary semiconductor device according to claim 9 , wherein the tantalum nitride layer has a thickness of 1 nm to 300 nm.
Claim 14
Dependent Claim
23 words
The complementary semiconductor device according to claim 9 , wherein the gate electrode further comprises a cap layer formed on the uppermost layer.
Claim 15
Dependent Claim
45 words
The complementary semiconductor device according to claim 12 , wherein the cap layer is formed of at least one material selected from TaN x , TaSi x N y , TiN x , TiAl x N y , Si, and silicide of a transition metal.
Claim 16
Dependent Claim
20 words
The complementary semiconductor device according to claim 13 , wherein the cap layer is formed of the tantalum nitride layer.
Claim 17
Dependent Claim
24 words
The complementary semiconductor device according to claim 9 , wherein silicide layers are formed on part of the first and second impurity diffusion layers.
Claim 18
Dependent Claim
27 words
The complementary semiconductor device according to claim 9 , wherein the semiconductor layer has a silicon on insulator (SOI) structure or a silicon on nothing (SON) structure.
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