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Salicide block for silicon-on-insulator (SOI) applications

Assignee: Advanced Micro Devices Inc
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Filing: 2001-04-25
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Granted: 2003-07-01
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Expires: 2021-04-25
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Abstract

Abstract A method is provided, the method comprising forming a buffer layer above a structure layer, and forming a dielectric layer above the buffer layer. The method also comprises patterning the dielectric layer to form a salicide block above a portion of the structure layer protecting the portion from a subsequent salicidation. A device is also provided, the device comprising a buffer layer above a structure layer and a dielectric layer above the buffer layer. The dielectric layer is patterned to form a salicide block above a portion of the structure layer to protect the portion from a subsequent salicidation.

Inventors

  • 👤 David Donggang Wu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 18:58
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6739; H10D30/674; H10D30/6741; H10D30/6743; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/811; H10D84/817; H10D86/00; H10D86/01; H10D86/201; H10D1/00; H10D1/40; H10D1/47

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 106 words
A method, comprising: providing a silicon-on-insulator structure comprising: a bulk substrate; a buried insulation layer; and an active layer; forming a polysilicon layer in the active layer of the silicon-on-insulator structure layer; forming a buffer layer above the polysilicon layer and at least a portion of the active layer; forming a dielectric layer above the buffer layer; and patterning the dielectric layer and the buffer layer to form a salicide block above the polysilicon layer and the at least a portion of the active layer said salicide block protecting the polysilicon layer and the at least a portion of the active layer from a subsequent salicidation.
Claim 2
Independent Claim 106 words
A method, comprising: providing a silicon-on-insulator structure comprising: a bulk substrate; a buried insulation layer; and an active layer; forming a polysilicon layer in the active layer of the silicon-on-insulator structure layer; forming a buffer layer above the polysilicon layer and at least a portion of the active layer; forming a dielectric layer above the buffer layer; and patterning the dielectric layer and the buffer layer to form a salicide block above the polysilicon layer and the at least a portion of the active layer said salicide block protecting the polysilicon layer and the at least a portion of the active layer from a subsequent salicidation.
Claim 3
Dependent Claim 17 words
The method of claim 1 , wherein forming the active layer comprises forming an epitaxial semiconductor layer.
Claim 4
Dependent Claim 23 words
The method of claim 1 , wherein forming the active layer comprises forming the active layer having a thickness of about 1000-5000 Å.
Claim 5
Dependent Claim 24 words
The method of claim 1 , wherein forming the polysilicon layer comprises forming an undoped polysilicon layer having a width of about 1000-2500 Å.
Claim 6
Dependent Claim 16 words
The method of claim 1 , wherein forming the polysilicon layer comprises forming a passive resistor.
Claim 7
Dependent Claim 23 words
The method of claim 1 , wherein forming the buffer layer comprises forming the buffer layer having a thickness of about 50-200 Å.
Claim 8
Dependent Claim 23 words
The method of claim 1 , wherein forming the dielectric layer comprises forming the dielectric layer having a thickness of about 100-900 Å.
Claim 9
Dependent Claim 24 words
The method of claim 1 , wherein forming the dielectric layer comprises forming the dielectric layer of silicon nitride (Si 3 N 4 ).
Claim 10
Dependent Claim 19 words
The method of claim 1 , further comprising forming at least one shallow trench isolation in the active layer.

References Cited (Backward Citations)

EP0145926A2 Cited
US5352923A Cited
US5930638A Cited
US5656524A Cited
JPH07321327A Cited
US6350652B1 Cited
WO2001006554A1 Cited
JP2001250869A Cited
US6365481B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2006-06-30 2006-12-30 2007-07-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2010-06-30 2010-12-30 2011-07-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2014-06-30 2014-12-30 2015-07-01 $7700.00 Window Closed / Lapsed

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