US6586294B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks
Assignee: Intel Corp
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Filing: 2002-01-02
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Granted: 2003-07-01
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Expires: 2022-01-02
Abstract
Abstract A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.
Inventors
- 👤 Ian R. Post
- 👤 Kaizad Mistry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:01
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
50 words
A method comprising: implanting a dopant into an NMOS transistor and a dopant into a PMOS transistor of a CMOS circuit to set a plurality of threshold voltages; and optimizing a high threshold voltage NMOS transistor and a low threshold voltage PMOS transistor with a single masking operation and implant.
Claim 2
Independent Claim
50 words
A method comprising: implanting a dopant into an NMOS transistor and a dopant into a PMOS transistor of a CMOS circuit to set a plurality of threshold voltages; and optimizing a high threshold voltage NMOS transistor and a low threshold voltage PMOS transistor with a single masking operation and implant.
Claim 3
Dependent Claim
18 words
The method of claim 1 , further comprising: implanting to set the threshold voltages with a halo implant.
Claim 4
Dependent Claim
32 words
The method of claim 1 , further comprising: implanting to set the low threshold voltage NMOS transistor with a halo implant of one of the group consisting of boron and boron diflouride.
Claim 5
Dependent Claim
32 words
The method of claim 1 , further comprising: implanting to set the high threshold voltage PMOS transistor with a halo implant of one of the group consisting of arsenic, phosphorous and antimony.
Claim 6
Dependent Claim
51 words
The method of claim 1 , further comprising: implanting such that the threshold voltage of the high threshold voltage NMOS transistor is enhanced, and the threshold voltage of the low threshold voltage PMOS transistor is compensated with a single halo implant of one of the group comprising boron and boron difluoride.
Claim 7
Dependent Claim
51 words
The method of claim 1 , further comprising: implanting such that the threshold voltage of the high threshold voltage PMOS transistor is enhanced, and the threshold voltage of the low threshold voltage NMOS transistor is compensated with a single halo implant of one of the group comprising arsenic, phosphorous and antimony.
Claim 8
Independent Claim
138 words
A method comprising: masking off a wafer containing CMOS circuits to expose NMOS transistors and cover PMOS transistors; performing a source drain extension implant on the NMOS transistors; performing a low threshold voltage first halo implantation on the NMOS transistors; masking off the wafer containing CMOS circuits to expose PMOS transistors and cover NMOS transistors; performing a source drain extension implant on the PMOS transistors; performing a high threshold voltage second halo implantation on the PMOS transistors; masking off the wafer containing CMOS circuits to expose high threshold voltage NMOS transistors and low threshold voltage PMOS transistors while covering low threshold voltage NMOS transistors and high threshold voltage PMOS transistors; and enhancing the threshold voltage of the high threshold voltage NMOS transistor while compensating the threshold of the low threshold voltage PMOS transistor with a single third implantation.
Claim 9
Independent Claim
138 words
A method comprising: masking off a wafer containing CMOS circuits to expose NMOS transistors and cover PMOS transistors; performing a source drain extension implant on the NMOS transistors; performing a low threshold voltage first halo implantation on the NMOS transistors; masking off the wafer containing CMOS circuits to expose PMOS transistors and cover NMOS transistors; performing a source drain extension implant on the PMOS transistors; performing a high threshold voltage second halo implantation on the PMOS transistors; masking off the wafer containing CMOS circuits to expose high threshold voltage NMOS transistors and low threshold voltage PMOS transistors while covering low threshold voltage NMOS transistors and high threshold voltage PMOS transistors; and enhancing the threshold voltage of the high threshold voltage NMOS transistor while compensating the threshold of the low threshold voltage PMOS transistor with a single third implantation.
Claim 10
Dependent Claim
25 words
The method of claim 7 , further comprising: implanting the first halo implantation to set the threshold voltage for the high threshold voltage NMOS transistor.
Claim 11
Dependent Claim
25 words
The method of claim 7 , further comprising: implanting the second halo implantation to set the threshold voltage for the low threshold voltage PMOS transistor.
Claim 12
Dependent Claim
37 words
The method of claim 7 , further comprising: implanting the third halo implantation to enhance the threshold voltage of the high threshold voltage PMOS transistor and compensate the threshold voltage of the low threshold voltage NMOS transistor.
Claim 13
Dependent Claim
11 words
The method of claim 7 , further comprising: masking with photoresist.
Claim 14
Dependent Claim
17 words
The method of claim 11 , further comprising: masking with photoresist which is about 0.5 microns thick.
Claim 15
Dependent Claim
58 words
The method of claim 7 , further comprising: implanting the first halo implant with a material comprising one of the group consisting of boron and boron difluoride implanted at a angle of about 0-60° from the normal to the wafer at a dose of about 1×10 13 to 1×10 14 atoms at an energy of about 5-50 keV.
Claim 16
Dependent Claim
58 words
The method of claim 7 , further comprising: implanting the second halo implant with a material comprising one of the group consisting of arsenic, phosphorous and antimony implanted at a angle of about 0-60° from the normal to the wafer at a dose of about 1×10 13 to 1×10 14 atoms at an energy of about 30-150 keV.
Claim 17
Dependent Claim
58 words
The method of claim 7 , further comprising: implanting the third halo implant with a material comprising one of the group consisting of boron and boron difluoride implanted at a angle of about 0-60° from the normal to the wafer at a dose of about 1×10 13 to 1×10 14 atoms at an energy of about 5-50 keV.
References Cited (Backward Citations)
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