Patent US6580118B2 successfully refreshed from Google Patents.
← Back to Patent Explorer
US6580118B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Non-volatile semiconductor memory cell having a metal oxide dielectric, and method for fabricating the memory cell

Assignee: Infineon Technologies AG
•
Filing: 2001-12-10
•
Granted: 2003-06-17
•
Expires: 2021-12-10
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A non-volatile semiconductor memory cell and an associated method are disclosed, in which a conventional dielectric ONO layer ( 10 ) is replaced by a very thin metal oxide layer ( 6 ) of WO x and/or TiO 2 . The high relative dielectric constant of these materials further improves the integration density and the control voltages required for the semiconductor memory cell.

Inventors

  • 👤 Christoph Ludwig
  • 👤 Martin Schrems

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 08:25
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10D; H10D64/00; H10D64/01; H10D64/031; H10D64/035

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 74 words
A non-volatile semiconductor memory cell, comprising: a semiconductor substrate; an insulating tunnel oxide layer; a conductive floating-gate layer; an insulating dielectric layer including at least one metal oxide layer and at least one Si 3 N 4 layer enclosing said metal oxide layer; and a conductive control-gate layer; said metal oxide layer being made of a material selected from the group consisting of WO x , where x=2 to 3, and TiO 2 .
Claim 2
Dependent Claim 74 words
A non-volatile semiconductor memory cell, comprising: a semiconductor substrate; an insulating tunnel oxide layer; a conductive floating-gate layer; an insulating dielectric layer including at least one metal oxide layer and at least one Si 3 N 4 layer enclosing said metal oxide layer; and a conductive control-gate layer; said metal oxide layer being made of a material selected from the group consisting of WO x , where x=2 to 3, and TiO 2 .
Claim 3
Dependent Claim 18 words
The non-volatile semiconductor memory cell according to claim 1 , wherein said floating-gate layer includes a poly-Si layer.
Claim 4
Dependent Claim 30 words
The non-volatile semiconductor memory cell according to claim 2 , wherein said floating-gate layer includes a layer selected from the group consisting of a TiN layer and a WN layer.
Claim 5
Dependent Claim 30 words
The non-volatile semiconductor memory cell according to claim 1 , wherein said floating-gate layer includes a layer selected from the group consisting of a TiN layer and a WN layer.
Claim 6
Dependent Claim 23 words
The non-volatile semiconductor memory cell according to claim 1 , wherein said dielectric layer has a thickness that is greater than 15 nm.
Claim 7
Dependent Claim 26 words
The non-volatile semiconductor memory cell according to claim 1 , wherein said floating-gate layer has a thickness in a range from 5 nm to 50 nm.
Claim 8
Independent Claim 96 words
A method for fabricating a non-volatile semiconductor memory cell, which comprises: a) forming active regions in a semiconductor substrate; b) forming a tunnel oxide layer; c) depositing a floating-gate layer; d) depositing a metal-containing layer that includes a material selected from the group consisting of a metal and a metal compound; e) etching the metal-containing layer and the floating-gate layer; f) oxidizing the metal-containing layer and exposed side regions of the floating-gate layer to form a dielectric layer; g) depositing a control-gate layer; and h) etching the control-gate layer, the dielectric layer, and the floating-gate layer.
Claim 9
Independent Claim 96 words
A method for fabricating a non-volatile semiconductor memory cell, which comprises: a) forming active regions in a semiconductor substrate; b) forming a tunnel oxide layer; c) depositing a floating-gate layer; d) depositing a metal-containing layer that includes a material selected from the group consisting of a metal and a metal compound; e) etching the metal-containing layer and the floating-gate layer; f) oxidizing the metal-containing layer and exposed side regions of the floating-gate layer to form a dielectric layer; g) depositing a control-gate layer; and h) etching the control-gate layer, the dielectric layer, and the floating-gate layer.
Claim 10
Dependent Claim 24 words
The method according to claim 7 , which comprises: in step c) depositing a TiN layer; and in step d) depositing a Ti layer.
Claim 11
Dependent Claim 29 words
The method according to claim 7 , which comprises: in step c) depositing a poly-Si layer; and in step d) depositing a WO x layer, where x=2 to 3.
Claim 12
Dependent Claim 53 words
The method according to claim 7 , which comprises: in steps c) and d) depositing a common tungsten-containing layer; and in step f) performing the oxidizing out until an oxidized partial layer of the tungsten-containing layer forms the dielectric layer and an unoxidized partial layer of the tungsten-containing layer forms the floating-gate layer.
Claim 13
Dependent Claim 22 words
The method according to claim 7 , which comprises: i) forming an insulating intermediate layer on the surface of the control-gate layer.
Claim 14
Dependent Claim 24 words
The method according to claim 11 , which comprises: in step c) depositing a TiN layer; and in step d) depositing a Ti layer.
Claim 15
Dependent Claim 29 words
The method according to claim 11 , which comprises: in step c) depositing a poly-Si layer; and in step d) depositing a WO x layer, where x=2 to 3.
Claim 16
Dependent Claim 53 words
The method according to claim 11 , which comprises: in steps c) and d) depositing a common tungsten-containing layer; and in step f) performing the oxidizing out until an oxidized partial layer of the tungsten-containing layer forms the dielectric layer and an unoxidized partial layer of the tungsten-containing layer forms the floating-gate layer.

References Cited (Backward Citations)

US4115914A Cited
US5268319A Cited
US5278087A Cited
US5102814A Cited
JPH07135202A Cited
US5836772A Cited
US5739566A Cited
US5907188A Cited
US6133150A Cited
US5998264A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2006-06-16 2006-12-16 2007-06-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2010-06-16 2010-12-16 2011-06-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2014-06-16 2014-12-16 2015-06-17 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag