Patent US6578154B1 successfully refreshed from Google Patents.
US6578154B1
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Clock duty cycle correction circuit which corrects an input clock by directly comparing the input clock with a reference clock generated by the output clock
Assignee: Malikie Innovations Ltd
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Filing: 2000-01-10
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Granted: 2003-06-10
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Expires: 2020-01-10
Abstract
Abstract A clock signal duty cycle control circuit is provided that receives an incoming signal from a clock signal input source and generates an improved output clock signal having an accurately controlled duty cycle. The circuit controls the duty cycle of the output clock signal by comparing the incoming signal to a reference value in a comparator. The reference value is derived from a reference charge stored on a capacitor. The reference charge is built up in the capacitor using the currents from a current source and a current sink, which are controlled using translated output signals from the comparator.
Inventors
- 👤 John Wynen
- 👤 Richard Madter
- 👤 Andrew Fergusson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:53
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156; H03K5/1565
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
138 words
An apparatus comprising: a clock source configured to generate a first clock signal having an undefined duty cycle; a clock signal duty cycle controller coupled to the clock source and configured to process the first clock signal and output a second clock signal having a precisely controlled duty cycle; and a clock signal utilizing device operatively coupled to the clock signal duty cycle controller, wherein the clock signal duty cycle controller includes a circuit configured to generate the second clock signal, the circuit comprising: a comparator; a signal processing device coupled to an output terminal of the comparator and operable to generate control signals; first and second current devices coupled to the signal processing device to receive the control signals; and a reference charge storage device operatively coupled between the first and second current devices and the comparator.
Claim 2
Independent Claim
138 words
An apparatus comprising: a clock source configured to generate a first clock signal having an undefined duty cycle; a clock signal duty cycle controller coupled to the clock source and configured to process the first clock signal and output a second clock signal having a precisely controlled duty cycle; and a clock signal utilizing device operatively coupled to the clock signal duty cycle controller, wherein the clock signal duty cycle controller includes a circuit configured to generate the second clock signal, the circuit comprising: a comparator; a signal processing device coupled to an output terminal of the comparator and operable to generate control signals; first and second current devices coupled to the signal processing device to receive the control signals; and a reference charge storage device operatively coupled between the first and second current devices and the comparator.
Claim 3
Dependent Claim
15 words
The apparatus of claim 1 , wherein the reference charge storage device is a capacitor.
Claim 4
Dependent Claim
24 words
The apparatus of claim 1 , wherein: the first current device is a current source; and the second current device is a current sink.
Claim 5
Dependent Claim
28 words
The apparatus of claim 3 , wherein: the first current device is a voltage controlled current source; and the second current device is a voltage controlled current sink.
Claim 6
Dependent Claim
32 words
The apparatus of claim 3 , wherein: the current source includes a pFET coupled to a capacitor and switches; and the current sink includes an nFET coupled to a capacitor and switches.
Claim 7
Independent Claim
166 words
An apparatus comprising: a clock source configured to generate a first clock signal having an undefined duty cycle; a clock signal duty cycle controller coupled to the clock source and configured to process the first clock signal and output a second clock signal having a precisely controlled duty cycle; and a clock signal utilizing device operatively coupled to the clock signal duty cycle controller; wherein the clock signal duty cycle controller includes a circuit configured to generate the second clock signal, the circuit comprising: a comparator; a signal processing device coupled to the comparator; first and second current devices coupled to the signal processing device; and a reference charge storage device operatively coupled between the first and second current devices and the comparator; and wherein: the reference charge storage device is coupled to a negative terminal of the comparator; the clock source is coupled to the positive terminal of the comparator; and the clock signal utilizing device is coupled to an output terminal of the comparator.
Claim 8
Independent Claim
166 words
An apparatus comprising: a clock source configured to generate a first clock signal having an undefined duty cycle; a clock signal duty cycle controller coupled to the clock source and configured to process the first clock signal and output a second clock signal having a precisely controlled duty cycle; and a clock signal utilizing device operatively coupled to the clock signal duty cycle controller; wherein the clock signal duty cycle controller includes a circuit configured to generate the second clock signal, the circuit comprising: a comparator; a signal processing device coupled to the comparator; first and second current devices coupled to the signal processing device; and a reference charge storage device operatively coupled between the first and second current devices and the comparator; and wherein: the reference charge storage device is coupled to a negative terminal of the comparator; the clock source is coupled to the positive terminal of the comparator; and the clock signal utilizing device is coupled to an output terminal of the comparator.
Claim 9
Dependent Claim
75 words
A clock signal duty cycle controller, comprising: a comparator configured to receive an input clock signal and a reference signal, and to output a precision controlled duty cycle clock signal; a signal processing device coupled to the output of the comparator; first and second current devices coupled to the signal processing device; and a reference charge storage device for generating a reference signal operatively coupled between the first and second current sources and the comparator.
Claim 10
Dependent Claim
75 words
A clock signal duty cycle controller, comprising: a comparator configured to receive an input clock signal and a reference signal, and to output a precision controlled duty cycle clock signal; a signal processing device coupled to the output of the comparator; first and second current devices coupled to the signal processing device; and a reference charge storage device for generating a reference signal operatively coupled between the first and second current sources and the comparator.
Claim 11
Dependent Claim
28 words
The controller of claim 7 , wherein: the first current device is a voltage controlled current source; and the second current device is a voltage controlled current sink.
Claim 12
Dependent Claim
24 words
The controller of claim 7 , wherein: the first current device is a current source; and the second current device is a current sink.
Claim 13
Dependent Claim
32 words
The controller of claim 9 , wherein: the current source includes a pFET coupled to a capacitor and switches; and the current sink includes a nFET coupled to a capacitor and switches.
Claim 14
Dependent Claim
70 words
The controller of claim 10 , wherein: the pFET and capacitor are configured to store a charge value proportional to a first current value when a first predetermined number of the switches are opened; the nFET and capacitor are configured to store a charge value proportional to a second current value when a first predetermined number of the switches are opened; and the first and second current values are identical.
Claim 15
Dependent Claim
103 words
The controller of claim 11 , wherein: the current source is configured to conduct current such that a current with the first current value flows to the reference charge storage device when a second predetermined number of the switches are opened; the current sink is configured to conduct current such that a current with the second current value flows to the reference charge storage device when a second predetermined number of the switches are opened; and the device outputs an output clock signal such that the output clock signal has a predetermined duty cycle based on the reference value input into the comparator.
Claim 16
Independent Claim
71 words
An apparatus configured to convert a curvilinear clock signal into a square-wave clock signal and to program current, comprising: a voltage controlled current source, the current source including a pFET coupled to first, second, and third source switches and a source capacitor; and a voltage controlled current sink, tile current sink including a nFET coupled to the pFET and coupled to first, second and third sink switches and a sink capacitor.
Claim 17
Independent Claim
71 words
An apparatus configured to convert a curvilinear clock signal into a square-wave clock signal and to program current, comprising: a voltage controlled current source, the current source including a pFET coupled to first, second, and third source switches and a source capacitor; and a voltage controlled current sink, tile current sink including a nFET coupled to the pFET and coupled to first, second and third sink switches and a sink capacitor.
Claim 18
Dependent Claim
132 words
A clock signal duty cycle controlling apparatus, comprising: means for generating a clock signal; means for receiving the clock signal, the means for receiving being configured to generate an output clock signal with a predetermined duty cycle based on the received clock signal, wherein the means for receiving comprises: means for comparing the received clock signal to a reference value in order to generate the output clock signal; means for translating the output clock signal to generate a plurality of second signals based on the output clock signal; means for producing a reference current, the means for producing a reference current operatively controlled by the plurality of second signals; and means for generating the reference value based on the reference current; and means for propagating logic based on the output clock signal.
Claim 19
Dependent Claim
132 words
A clock signal duty cycle controlling apparatus, comprising: means for generating a clock signal; means for receiving the clock signal, the means for receiving being configured to generate an output clock signal with a predetermined duty cycle based on the received clock signal, wherein the means for receiving comprises: means for comparing the received clock signal to a reference value in order to generate the output clock signal; means for translating the output clock signal to generate a plurality of second signals based on the output clock signal; means for producing a reference current, the means for producing a reference current operatively controlled by the plurality of second signals; and means for generating the reference value based on the reference current; and means for propagating logic based on the output clock signal.
Claim 20
Dependent Claim
60 words
The apparatus of claim 14 , wherein: during a first mode of operation the means for producing a reference current is configured to be programmed; and during a second mode of operation the means for producing a reference current is configured such that, based on the programming, two identical currents are generated that are combined to produce the reference current.
Claim 21
Independent Claim
82 words
A method comprising the steps of: receiving a clock signal with an undefined duty cycle; generating an output clock signal with a predetermined duty cycle by: (A) comparing the received clock signal to a reference value in order to generate the output clock signal; (B) translating the output clock signal to generate a plurality of second signals based on the output clock signal; (C) utilising the plurality of second signals to control first and second current devices that generate the reference value.
Claim 22
Independent Claim
82 words
A method comprising the steps of: receiving a clock signal with an undefined duty cycle; generating an output clock signal with a predetermined duty cycle by: (A) comparing the received clock signal to a reference value in order to generate the output clock signal; (B) translating the output clock signal to generate a plurality of second signals based on the output clock signal; (C) utilising the plurality of second signals to control first and second current devices that generate the reference value.
Claim 23
Independent Claim
176 words
An apparatus comprising: a clock source configured to generate a first clock signal having an undefined duty cycle; a clock signal duty cycle controller coupled to the clock source and configured to process the first clock signal and output a second clock signal having a precisely controlled duty cycle; and a clock signal utilizing device operatively coupled to the clock signal duty cycle controller; wherein the clock signal duty cycle controller includes a circuit configured to generate the second clock signal, the circuit comprising: a comparator operable to output at an output terminal the second clock signal having the precisely controlled duty cycle; a signal processing device coupled to the output terminal of the comparator and operable to generate control signals; a current device coupled to the signal processing device and operable to control a current in response to the control signals generated by the signal processing device; and a reference charge storage device operatively coupled to the current device and operable to store a charge in response to the current controlled by the current device.
Claim 24
Independent Claim
176 words
An apparatus comprising: a clock source configured to generate a first clock signal having an undefined duty cycle; a clock signal duty cycle controller coupled to the clock source and configured to process the first clock signal and output a second clock signal having a precisely controlled duty cycle; and a clock signal utilizing device operatively coupled to the clock signal duty cycle controller; wherein the clock signal duty cycle controller includes a circuit configured to generate the second clock signal, the circuit comprising: a comparator operable to output at an output terminal the second clock signal having the precisely controlled duty cycle; a signal processing device coupled to the output terminal of the comparator and operable to generate control signals; a current device coupled to the signal processing device and operable to control a current in response to the control signals generated by the signal processing device; and a reference charge storage device operatively coupled to the current device and operable to store a charge in response to the current controlled by the current device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-06-09 | 2006-12-09 | 2007-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-06-09 | 2010-12-09 | 2011-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-06-09 | 2014-12-09 | 2015-06-10 | $7700.00 | Window Closed / Lapsed |