Method and apparatus for gating interrupts in a computing system

Claim 2

An interrupt gating module comprises: an interrupt register operable to store an indication of activation for each of a plurality of interrupts; a masking register operable to store masking information for each of the plurality of interrupts; first logic circuitry operably coupled to a first portion of the interrupt register that corresponds to a first portion of the plurality of interrupts and to a first portion of the masking register that corresponds to the first portion of the plurality of interrupts, wherein the first logic circuitry provides a first indication as to whether at least one interrupt of the first portion of interrupts is active; second logic circuitry operably coupled to a second portion of the interrupt register that corresponds to a second portion of the plurality of interrupts and to a second portion of the masking register that corresponds to the second portion of the plurality of interrupts, wherein the second logic circuitry provides a second indication as to whether at least one interrupt of the second portion of interrupts is active; and enable circuitry operably coupled to the first and second logic circuitry and is operably coupled to receive an enable/disable signal, wherein the enable circuitry masks the first and second indications when the enable/disable signal is disabled.

Claim 3

The interrupt gating module of claim 1 further comprises: third logic circuitry operably coupled to a third portion of the interrupt register that corresponds to a third portion of the plurality of interrupts and to a third portion of the masking register that corresponds to the third portion of the plurality of interrupts, wherein the third logic circuitry provides a third indication as to whether at least one interrupt of the third portion of interrupts is active, wherein the enable circuitry masks the third indication when the enable/disable signal is disabled.

Claim 4

The interrupt gating module of claim 1 , wherein the interrupt register further comprises a plurality of register locations, wherein each register location of the plurality of register locations maps to a corresponding one of the plurality of interrupts.

Claim 5

The interrupt gating module of claim 3 , wherein the corresponding ones of the plurality of interrupts that map to the first portion of the interrupt register having a higher priority than the corresponding ones of the plurality of interrupts that map to the second portion of the interrupt register.

Claim 6

The interrupt gating module of claim 3 , wherein the plurality of interrupts includes system event interrupts, external device interrupts, inter-processor interrupts, and intra-processor interrupts.

Claim 7

The interrupt gating module of claim 5 , wherein the registers locations that map to the inter-processor interrupts and to the intra-processor interrupts are read/write register locations with respect to a processor and the register locations that map to the system event interrupts and the external device interrupts are read register locations with respect to the processor.

Claim 8

The interrupt gating module of claim 1 , wherein the interrupt register further comprises a plurality of latching circuits that latch the indication of activation for the each of the plurality of interrupts.

Claim 9

The interrupt gating module of claim 1 further comprises: third logic circuitry; fourth logic circuitry; and second enable circuitry, wherein the interrupt register stores the indication of activation for each of a first and second plurality of interrupts, wherein the first plurality of interrupts are for a first processor and the second plurality of interrupts are for a second processor; wherein the masking register stores the masking information for each of the first and second plurality of interrupts; wherein the first logic circuitry is operably coupled to the first portion of the interrupt register that corresponds to a first portion of the first plurality of interrupts and to the first portion of the masking register that corresponds to the first portion of the first plurality of interrupts; wherein the second logic circuitry is operably coupled to the second portion of the interrupt register that corresponds to a second portion of the first plurality of interrupts and to the second portion of the masking register that corresponds to the second portion of the first plurality of interrupts; wherein the third logic circuitry is operably coupled to a third portion of the interrupt register that corresponds to a first portion of the second plurality of interrupts and to a third portion of the masking register that corresponds to the first portion of the second plurality of interrupts, wherein the third logic circuitry provides a third indication as to whether at least one interrupt of the first portion of the second plurality of interrupts is active; and wherein the fourth logic circuitry is operably coupled to a fourth portion of the interrupt register that corresponds to a second portion of the second plurality of interrupts and to a fourth portion of the masking register that corresponds to the second portion of the second plurality of interrupts, wherein the fourth logic circuitry provides a fourth indication as to whether at least one interrupt of the second portion of the second plurality of interrupts is active.

Claim 12

The method of claim 9 further comprises: providing a second indication as to whether at least one interrupt of a second portion of the plurality of interrupts is active based on a corresponding second portion of the masking information; and masking the second indication when a second enable/disable signal is disabled.

Claim 13

The method of claim 10 further comprises: providing a third indication as to whether at least one interrupt of a third portion of the plurality of interrupts is active based on a corresponding third portion of the masking information; and masking the third indication when a third enable/disable signal is disabled.

Claim 14

The method of claim 10 further comprises establishing the first portion of the plurality of interrupts to have a higher priority than the second portion of the plurality of interrupts.

Claim 15

The method of claim 9 , wherein the plurality of interrupts includes system event interrupts, external device interrupts, inter-processor interrupts, and intra-processor interrupts.

Claim 16

The method of claim 9 further comprises: storing a second indication of activation for each of a second plurality of interrupts for a second processor; storing second masking information for each of the second plurality of interrupts for a second processor; providing an indication as to whether at least one interrupt of a first portion of the second plurality of interrupts is active based on a corresponding first portion of the second masking information; and masking the indication when a second enable/disable signal is disabled.

Claim 17

An interrupt gating module comprises: a processing module; and memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to: (a) store an indication of activation for each of a plurality of interrupts; (b) store masking information for each of the plurality of interrupts; (c) provide a first indication as to whether at least one interrupt of a first portion of the plurality of interrupts is active based on a corresponding first portion of the masking information; and (d) mask the first indication when an enable/disable signal is disabled.

Claim 18

An interrupt gating module comprises: a processing module; and memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to: (a) store an indication of activation for each of a plurality of interrupts; (b) store masking information for each of the plurality of interrupts; (c) provide a first indication as to whether at least one interrupt of a first portion of the plurality of interrupts is active based on a corresponding first portion of the masking information; and (d) mask the first indication when an enable/disable signal is disabled.

Claim 19

The interrupt gating module of claim 15 , wherein the memory further comprises operational instructions that cause the processing module to: provide a second indication as to whether at least one interrupt of a second portion of the plurality of interrupts is active based on a corresponding second portion of the masking information; and mask the second indication when a second enable/disable signal is disabled.

Claim 20

The interrupt gating module of claim 16 , wherein the memory further comprises operational instructions that cause the processing module to: provide a third indication as to whether at least one interrupt of a third portion of the plurality of interrupts is active based on a corresponding third portion of the masking information; and mask the third indication when a third enable/disable signal is disabled.

Claim 21

The interrupt gating module of claim 16 , wherein the memory further comprises operational instructions that cause the processing module to establish the first portion of the plurality of interrupts to have a higher priority than the second portion of the plurality of interrupts.

Claim 22

The interrupt gating module of claim 15 , wherein the plurality of interrupts includes system event interrupts, external device interrupts, inter-processor interrupts, and intra-processor interrupts.

Claim 23

The interrupt gating module of claim 15 , wherein the memory further comprises operational instructions that cause the processing module to: store a second indication of activation for each of a second plurality of interrupts for a second processor; store second masking information for each of the second plurality of interrupts for a second processor; provide an indication as to whether at least one interrupt of a first portion of the second plurality of interrupts is active based on a corresponding first portion of the second masking information; and mask the indication when a second enable/disable signal is disabled.