US6570206B1
Expired / Lapsed
US
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Semiconductor device
Assignee: Hitachi Ltd
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Filing: 2000-03-29
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Granted: 2003-05-27
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Expires: 2020-03-29
Abstract
Abstract In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment accuracy is considered. In order to achieve integration similarly to that of 1T1C cells by using gain cells, a memory cell block constituted as follows is used. A memory block (MCT) comprises a plurality of memory cells (MC 0 -MC 3 ). Each memory cell includes a PMOS transistor (M 0 ) for writing and an NMOS transistor (M 1 ) for reading, and information is stored by holding electric charge in a storage node. The write transistors (M 0 ) are arranged in parallel in a plurality of cells, each source-drain path is connected to a data line (DL). The read transistors (M 1 ) are connected in series in a plurality of cells, and are connected to the data line (DL) via a block selection transistor (MB).
Inventors
- 👤 Takeshi Sakata
- 👤 Satoru Hanzawa
- 👤 Hideyuki Matsuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:39
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
141 words
A semiconductor device comprising: a data line; a first wordline crossing said data line; a second wordline crossing said data line; a first memory cell provided on the crossing point of said data line and said first wordline; and a second memory cell provided on the crossing point of said data line and said second wordline, wherein said first memory cell has: a first transistor being a signal path at writing; a second transistor being a signal path at reading; and a first storage node holding information by storing electric charge, said second memory cell has: a third transistor being a signal path at writing; a fourth transistor being a signal path at reading; and a second storage node holding information by storing electric charge, the read signal path from said fourth transistor to said data line includes said second transistor.
Claim 2
Dependent Claim
141 words
A semiconductor device comprising: a data line; a first wordline crossing said data line; a second wordline crossing said data line; a first memory cell provided on the crossing point of said data line and said first wordline; and a second memory cell provided on the crossing point of said data line and said second wordline, wherein said first memory cell has: a first transistor being a signal path at writing; a second transistor being a signal path at reading; and a first storage node holding information by storing electric charge, said second memory cell has: a third transistor being a signal path at writing; a fourth transistor being a signal path at reading; and a second storage node holding information by storing electric charge, the read signal path from said fourth transistor to said data line includes said second transistor.
Claim 3
Dependent Claim
33 words
The semiconductor device according to claim 1 , wherein the gate of said first transistor is connected to said first wordline, the gate of said third transistor is connected to said second wordline.
Claim 4
Dependent Claim
55 words
The semiconductor device according to claim 1 , wherein one source/drain terminal of said first transistor is connected to said data line and the other is connected to said first storage node, one source/drain terminal of said third transistor is connected to said data line, and the other is connected to said second storage node.
Claim 5
Dependent Claim
41 words
The semiconductor device according to claim 1 , wherein said first transistor and said second transistor are of a conduction type opposite to each other, said third transistor and said fourth transistor are of a conduction type opposite to each other.
Claim 6
Dependent Claim
57 words
The semiconductor device according to claim 1 , wherein said first memory cell further has a fifth transistor whose source and drain are connected to the source and drain of said second transistor, said second memory cell further has a sixth transistor whose source and drain are connected to the source and drain of said fourth transistor.
Claim 7
Dependent Claim
35 words
The semiconductor device according to claim 5 , wherein said second transistor and said fifth transistor are of the same conduction type, said fourth transistor and said sixth transistor are of the same conduction type.
Claim 8
Dependent Claim
33 words
The semiconductor device according to claim 5 , wherein the gate of said fifth transistor is connected to said first wordline, the gate of said sixth transistor is connected to said second wordline.
Claim 9
Dependent Claim
69 words
The semiconductor device according to claim 5 , wherein said fifth transistor is non-conductive in a period during which said first transistor is conductive, said first transistor is non-conductive in a period during which said fifth transistor is conductive, said sixth transistor is non-conductive in a period during which said second transistor is conductive, said second transistor is non-conductive in a period during which said sixth transistor is conductive.
Claim 10
Dependent Claim
35 words
The semiconductor device according to claim 5 , wherein said fifth transistor is provided on the side wall of said second transistor, said sixth transistor is provided on the side wall of said fourth transistor.
Claim 11
Dependent Claim
45 words
The semiconductor device according to claim 1 , wherein said first memory cell further has a first capacitance between said first wordline and said first storage node, said second memory cell further has a second capacitance between said second wordline and said second storage node.
Claim 12
Dependent Claim
64 words
The semiconductor device according to claim 1 , further comprising: a block selection line crossing said data line; and a seventh transistor whose gate is connected to said block selection line, wherein the read signal path from said second transistor to said data line includes said seventh transistor, the read signal path from said fourth transistor to said data line includes said seventh transistor.
Claim 13
Dependent Claim
160 words
A semiconductor device comprising: a write data line; a read data line; a first wordline crossing said write data line and said read data line; a second wordline crossing said write data line and said read data line; a first memory cell provided on the crossing point of said write data line and said first wordline; and a second memory cell provided on the crossing point of said write data line and said second wordline, wherein said first memory cell has: a first transistor being a signal path at writing; a second transistor being a signal path at reading; and a first storage node holding,information by storing electric charge, said second memory cell has: a third transistor being a signal path at writing; a fourth transistor being a signal path at reading; and a second storage node holding information by storing electric charge, the read signal path from said fourth transistor to said read data line includes said second transistor.
Claim 14
Dependent Claim
160 words
A semiconductor device comprising: a write data line; a read data line; a first wordline crossing said write data line and said read data line; a second wordline crossing said write data line and said read data line; a first memory cell provided on the crossing point of said write data line and said first wordline; and a second memory cell provided on the crossing point of said write data line and said second wordline, wherein said first memory cell has: a first transistor being a signal path at writing; a second transistor being a signal path at reading; and a first storage node holding,information by storing electric charge, said second memory cell has: a third transistor being a signal path at writing; a fourth transistor being a signal path at reading; and a second storage node holding information by storing electric charge, the read signal path from said fourth transistor to said read data line includes said second transistor.
Claim 15
Dependent Claim
24 words
The semiconductor device according to claim 12 , wherein said write data line and said read data line are formed by different wiring layers.
Claim 16
Dependent Claim
28 words
The semiconductor device according to claim 13 , wherein said read data line is formed by a wiring layer above a wiring layer of said write data line.
Claim 17
Dependent Claim
34 words
The semiconductor device according to claim 1 , wherein said first transistor and said third transistor have respective source and drain paths formed in the direction vertical to the surface of a semiconductor substrate.
Claim 18
Dependent Claim
49 words
The semiconductor device according to claim 15 , wherein said first wordline passes through the top portion of the source terminal and the drain terminal of said first transistor, said second wordline passes through the top portion of the source terminal and the drain terminal of said third transistor.
Claim 19
Dependent Claim
45 words
The semiconductor device according to claim 1 , wherein said first transistor and said third transistor have a first diffusion barrier film between the source terminal and a channel region and a second diffusion barrier film between the drain terminal and a channel region, respectively.
Claim 20
Dependent Claim
24 words
The semiconductor device according to claim 1 , wherein the channel regions of said first transistor and said third transistor are formed by polysilicon.
Claim 21
Dependent Claim
14 words
The semiconductor device according to claim 17 , wherein said polysilicon is intrinsic polysilicon.
Claim 22
Dependent Claim
30 words
The semiconductor device according to any one of claims 1 to 19 , which is synchronized with an external clock and fetches an address and a command to transmit/receive data.
References Cited (Backward Citations)
DE3543937A1
Cited
EP0224213A2
Cited
JPH03224265A
Cited
JPH043463A
Cited
JPH04147490A
Cited
US5606189A
Cited
JPH08250673A
Cited
US5675160A
Cited
JP2000113683A
Cited
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