Abstract In a DRAM memory cell comprising one capacitor having a capacitor electrode and an opposing electrode, and one insulated gate field effect transistor formed in a semiconductor substrate and having a pair of source/drain regions, one of which is connected to the capacitor electrode of the capacitor. A double gate thin film transistor having the same channel conductivity type as that of the insulated gate field effect transistor, is formed above the insulated gate field effect transistor. A first gate electrode of the thin film transistor is constituted of a gate electrode of the insulated gate field effect transistor, and a second gate electrode of the thin film transistor is constituted of the capacitor electrode of the capacitor. A source region of the thin film transistor and the other of the pair of source/drain regions of the insulated gate field effect transistor is connected to a bit line, and a drain region of the thin film transistor is connected to a power supply line.
Inventors
👤 Ryuichi Oikawa
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-31 10:53
CPC Classifications
H; H10; H10B; H10B12/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
177 words
A semiconductor memory comprising one capacitor having a capacitor electrode and an opposing electrode, one insulated gate field effect transistor formed in a semiconductor substrate and having a gate electrode connected to a word line and a pair of source/drain regions, one of said pair of source/drain regions being connected to said capacitor electrode of said capacitor, and a thin film transistor formed above said insulated gate field effect transistor and having the same channel conductivity type as that of said insulated gate field effect transistor, said thin film transistor having a first gate electrode and a second gate electrode, said first gate electrode being constituted of said gate electrode of said insulated gate field effect transistor, said second gate electrode being constituted of said capacitor electrode of said capacitor, a source region of said thin film transistor being connected to the other of said pair of source/drain regions of said insulated gate field effect transistor and to a bit line, and a drain region of said thin film transistor being connected to a power supply line.
Claim 2
Dependent Claim
177 words
A semiconductor memory comprising one capacitor having a capacitor electrode and an opposing electrode, one insulated gate field effect transistor formed in a semiconductor substrate and having a gate electrode connected to a word line and a pair of source/drain regions, one of said pair of source/drain regions being connected to said capacitor electrode of said capacitor, and a thin film transistor formed above said insulated gate field effect transistor and having the same channel conductivity type as that of said insulated gate field effect transistor, said thin film transistor having a first gate electrode and a second gate electrode, said first gate electrode being constituted of said gate electrode of said insulated gate field effect transistor, said second gate electrode being constituted of said capacitor electrode of said capacitor, a source region of said thin film transistor being connected to the other of said pair of source/drain regions of said insulated gate field effect transistor and to a bit line, and a drain region of said thin film transistor being connected to a power supply line.
Claim 3
Dependent Claim
23 words
A semiconductor memory claimed in claim 1 wherein said drain region of said thin film transistor constitutes said opposing electrode of said capacitor.
Claim 4
Dependent Claim
43 words
A semiconductor memory claimed in claim 1 wherein said capacitor is formed in a trench formed in a surface of said semiconductor substrate, and said opposing electrode of said capacitor is fixed to a potential different from that of said power supply line.