EP0224213A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: NEC Corp
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Filing: 1986-11-21
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Granted: —
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Expires: 2006-11-21
Abstract
Abstract A semiconductor memory device comprising a memory array section in which a plurality of memory cells are provided and a peripheral circuit section in which many circuit elements are provided is disclosed. The memory array section is substantially surrounded by a capacitor.
Inventors
- 👤 Akira C/O Nec Corporation Tamakoshi
- 👤 Yasukazu C/O Nec Corporation Inoue
- 👤 Muneyuki C/O Nec Corporation Hagiwara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 21:08
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
65 words
A semiconductor memory device comprising a semiconductor substrate, a memory cell array section provided in a first portion of said substrate and having a plurality of memory cells therein, a peripheral circuit section provided in a second portion of said substrate in the vicinity of said first portion and with a peripheral circuit formed therein, and a capacitor substantially surrounding said memory cell array section.
Claim 2
Dependent Claim
65 words
A semiconductor memory device comprising a semiconductor substrate, a memory cell array section provided in a first portion of said substrate and having a plurality of memory cells therein, a peripheral circuit section provided in a second portion of said substrate in the vicinity of said first portion and with a peripheral circuit formed therein, and a capacitor substantially surrounding said memory cell array section.
Claim 3
Dependent Claim
57 words
A semiconductor memory device comprising a semiconductor substrate having a major surface, a memory cell including a switching transistor and a storage capacitor coupled to said switching transistor, a circuit element belonging to a peripheral circuit, and an isolation capacitor positioned between said storage capacitor of said memory cell and said circuit element in said peripheral circuit.
Claim 4
Dependent Claim
57 words
A semiconductor memory device comprising a semiconductor substrate having a major surface, a memory cell including a switching transistor and a storage capacitor coupled to said switching transistor, a circuit element belonging to a peripheral circuit, and an isolation capacitor positioned between said storage capacitor of said memory cell and said circuit element in said peripheral circuit.
Claim 5
Dependent Claim
98 words
A semiconductor memory device of Claim 2, in which said storage capacitor is formed in a first trench extending from said major surface of said substrate inward said substrate with a dielectric film attached to the side and bottom surfaces of said first trench and an upper electrode provided on said dielectric film, and said isolation capacitor is formed in a second trench extending from said major surface of said substrate inward said substrate with a dielectric film attached to the side and bottom surfaces of said second trench and an upper electrode provided on said dielectric film.
Claim 6
Dependent Claim
23 words
A semiconductor memory device of Claim 3, in which the depth of said second trench is equal to that of said first trench.
Claim 7
Dependent Claim
23 words
A semiconductor memory device of Claim 3, in which the depth of said second trench is deeper than that of said first trench.
Claim 8
Dependent Claim
47 words
A semiconductor memory device of Claim 2, in which said storage capacitor of said memory cell is formed along the flat major surface of said substrate, and said capacitor between said storage capacitor and said circuit element is formed along the flat major surface of said substrate.
Claim 9
Dependent Claim
30 words
A semiconductor memory device of Claim 3 further comprising an impurity region having the conductivity type opposite to that of said substrate formed in said substrate under said upper electrode.
Claim 10
Dependent Claim
28 words
A semiconductor memory device of Claim 7, in which said impurity region is an inversion layer produced when a power supply voltage is applied to said upper electrode.
Claim 11
Dependent Claim
28 words
A semiconductor memory device of Claim 8, in which said substrate is of P-type and said impurity region is of N-type, the polarity of said voltage being positive.
References Cited (Backward Citations)
No citation records indexed.
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