US6567921B1
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US
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Asynchronous low power mode bus controller circuit and method of low power mode operation
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1999-01-25
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Granted: 2003-05-20
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Expires: 2019-01-25
Abstract
Abstract An asynchronous logic circuit allows a host Controller or hub to enter a low power state with its clock suspended. When a power manager calls for a low power state, the clock in the host or hub is suspended and the asynchronous logic circuit is engaged. The asynchronous logic circuit can detect events on the port while the host or hub is in the low power mode. The asynchronous logic circuit generates a downstream signal if required and sends out a wake up signal to the power manager. After the host or hub is awake, the host or hub regains control of the bus and the asynchronous logic circuit is disengaged.
Inventors
- 👤 James Edward Guziak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:00
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/325; G06F1/3253; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
69 words
A bus controller comprising: a Universal Serial Bus port; an asynchronous logic circuit coupled to the Universal Serial Bus port; and a clock circuit; wherein the asynchronous logic circuit is adapted to detect an event at the Universal Serial Bus port, cause the clock circuit to change from a sleeping state to a wake state, and transmit an acknowledgment signal until the clock circuit has entered the wake state.
Claim 2
Dependent Claim
69 words
A bus controller comprising: a Universal Serial Bus port; an asynchronous logic circuit coupled to the Universal Serial Bus port; and a clock circuit; wherein the asynchronous logic circuit is adapted to detect an event at the Universal Serial Bus port, cause the clock circuit to change from a sleeping state to a wake state, and transmit an acknowledgment signal until the clock circuit has entered the wake state.
Claim 3
Dependent Claim
35 words
The bus controller of claim 1 further comprising a clocked bus controller wherein the logic circuit is further adapted to cause the clocked bus controller to change from a sleeping state to a wake state.
Claim 4
Dependent Claim
22 words
The bus controller of claim 2 wherein the acknowledgment signal is transmitted until the clocked bus controller has entered the wake state.
Claim 5
Dependent Claim
29 words
The bus controller of claim 1 wherein the acknowledgement signal is transmitted, within the time specified by the USB specification, until the clock circuit has entered the wake state.
Claim 6
Dependent Claim
15 words
The bus controller of claim 4 wherein the acknowledgement signal is a downstream RESUME signal.
Claim 7
Dependent Claim
37 words
The bus controller of claim 1 further comprising: a power management circuit adapted to, when a low power mode is indicated, to cause the clock circuit to enter a sleep state and to enable the logic circuit.
Claim 8
Dependent Claim
63 words
A computer including a bus controller and a bus, the bus controller comprising: an asynchronous logic circuit; and a clock circuit; wherein the asynchronous logic circuit is adapted to detect an event on the bus, cause the clock circuit to change from a sleeping state to a wake state, and transmit an acknowledgment signal until the clock circuit has entered the wake state.
Claim 9
Dependent Claim
63 words
A computer including a bus controller and a bus, the bus controller comprising: an asynchronous logic circuit; and a clock circuit; wherein the asynchronous logic circuit is adapted to detect an event on the bus, cause the clock circuit to change from a sleeping state to a wake state, and transmit an acknowledgment signal until the clock circuit has entered the wake state.
Claim 10
Dependent Claim
35 words
The computer of claim 7 further comprising: a power management circuit adapted to, when a low power mode is indicated, cause the clock circuit to enter a sleep state and to enable the logic circuit.
Claim 11
Dependent Claim
98 words
A clocked bus controller comprising: a power manager; and an asynchronous logic circuit; the power manager adapted to: recognize that a low power mode is indicated, enable, upon recognition of the low power mode, the asynchronous logic circuit, and suspend, upon recognition of the low power mode, a clock signal in the clocked bus controller; the asynchronous logic circuit adapted to: detect activity on a bus port, produce, upon detection of activity, an acknowledgment signal upon detecting activity until the clocked bus controller is enabled, enable, upon detection of activity, the clock signal in the clocked bus controller.
Claim 12
Dependent Claim
98 words
A clocked bus controller comprising: a power manager; and an asynchronous logic circuit; the power manager adapted to: recognize that a low power mode is indicated, enable, upon recognition of the low power mode, the asynchronous logic circuit, and suspend, upon recognition of the low power mode, a clock signal in the clocked bus controller; the asynchronous logic circuit adapted to: detect activity on a bus port, produce, upon detection of activity, an acknowledgment signal upon detecting activity until the clocked bus controller is enabled, enable, upon detection of activity, the clock signal in the clocked bus controller.
Claim 13
Independent Claim
88 words
A method of using an asynchronous logic circuit for detecting and responding to bus events for use with a clocked bus controller capable of low power mode, the method comprising: (a) detecting activity on a bus port; (b) responding, upon detecting activity, until the clocked bus controller is ready; (c) sending a wake up signal to a power manager; and (d) passing control from the asynchronous logic circuit to the clocked bus controller once the clocked bus controller is ready and low power mode is no longer indicated.
Claim 14
Independent Claim
88 words
A method of using an asynchronous logic circuit for detecting and responding to bus events for use with a clocked bus controller capable of low power mode, the method comprising: (a) detecting activity on a bus port; (b) responding, upon detecting activity, until the clocked bus controller is ready; (c) sending a wake up signal to a power manager; and (d) passing control from the asynchronous logic circuit to the clocked bus controller once the clocked bus controller is ready and low power mode is no longer indicated.
Claim 15
Dependent Claim
32 words
The method of claim 10 further comprising: (f) recognizing that low power mode is indicated; (g) enabling the asynchronous logic circuit; and (h) suspending a clock signal in the clocked bus controller.
Claim 16
Dependent Claim
17 words
The method of claim 11 wherein steps (f) through (h) occur prior to steps (a) through (e).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-05-19 | 2006-11-18 | 2007-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-19 | 2010-11-18 | 2011-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-19 | 2014-11-18 | 2015-05-20 | $7700.00 | Window Closed / Lapsed |