US5630145A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for reducing power consumption according to bus activity as determined by bus access times
Assignee: United Microelectronics Corp
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Filing: 1995-05-05
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Granted: 1997-05-13
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Expires: 2015-05-05
Abstract
Abstract A power conservation computer architecture is provided for disabling a clock signal to all peripheral devices and bus controllers located on a plurality of Peripheral Component Interconnect (PCI) buses when it is determined that all of the PCI buses are idle. The PCI buses are determined to be idle through the use of a Power Management Unit (PMU) controller connected to the first of the plurality of PCI buses. The PMU controller first determines and stores in memory a time constant corresponding to the amount of time required for the PMU controller to read the head configuration of the farthest peripheral device from the PMU controller when there is no activity on any of the buses. Then, during the operation of the computer architecture, if the first PCI bus is determined to be idle, a comparison is made between the time constant and a measurement of the length of time required to read the head configuration of the farthest peripheral device from the PMU controller. If the time to access the head configuration is less than the time constant plus a predetermined time constant, thereby indicating that there is no activity on any of the PCI buses, a clock signal from the PMU controller is stopped, thus placing the bus controllers and peripheral devices in a reduced power consumption state. The clock signal to the bus controllers and peripheral devices is resumed by the PMU controller when an asynchronous signal is sent from the peripheral devices or bus controllers to the PMU controller to indicate that data exchange on the PCI buses will be occurring.
Inventors
- 👤 David Y. Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:43
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/3234; G06F1/325; G06F1/3253; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
207 words
A power management method for a computer, the computer including a plurality of Peripheral Component Interconnect (PCI) buses, a plurality of bus controllers for controlling the PCI buses, each bus controller being capable of generating an asynchronous signal, a plurality of peripheral devices connected to the PCI buses, each peripheral device being capable of generating an asynchronous signal, a Power Management Unit (PMU) controller connected to a first of the PCI buses the PMU controller being capable of detecting an asynchronous signal generated by any one of the bus controllers or peripheral devices, the method comprising the steps of: sending clock pulses to the peripheral devices, storing a first time constant in a memory, reading a head configuration of a peripheral device to obtain a second time constant, detecting an asynchronous signal generated by any one of the bus controllers or peripheral devices, stopping the sending of a clock signal to the bus controllers and the peripheral devices when the second time constant is smaller than the first time constant plus a predetermined time constant greater than or equal to zero, and restarting the clock signal when the asynchronous signal generated by any one of the bus controllers or peripheral devices is detected by the PMU controller.
Claim 2
Dependent Claim
207 words
A power management method for a computer, the computer including a plurality of Peripheral Component Interconnect (PCI) buses, a plurality of bus controllers for controlling the PCI buses, each bus controller being capable of generating an asynchronous signal, a plurality of peripheral devices connected to the PCI buses, each peripheral device being capable of generating an asynchronous signal, a Power Management Unit (PMU) controller connected to a first of the PCI buses the PMU controller being capable of detecting an asynchronous signal generated by any one of the bus controllers or peripheral devices, the method comprising the steps of: sending clock pulses to the peripheral devices, storing a first time constant in a memory, reading a head configuration of a peripheral device to obtain a second time constant, detecting an asynchronous signal generated by any one of the bus controllers or peripheral devices, stopping the sending of a clock signal to the bus controllers and the peripheral devices when the second time constant is smaller than the first time constant plus a predetermined time constant greater than or equal to zero, and restarting the clock signal when the asynchronous signal generated by any one of the bus controllers or peripheral devices is detected by the PMU controller.
Claim 3
Dependent Claim
24 words
The power management method of claim 1, further comprising the step of determining the first time constant during a power-on-self-test process of the computer.
Claim 4
Dependent Claim
39 words
The power management method of claim 1, wherein the first time constant corresponds to the time needed for the PMU controller to read the head configuration when all the peripheral devices other than the specific peripheral device are disabled.
Claim 5
Dependent Claim
39 words
The power management method of claim 1, wherein the head configuration is the head configuration of a peripheral device which is connected to a PCI bus which has the most intervening buses between itself and the first PCI bus.
Claim 6
Dependent Claim
21 words
The power management method of claim 1, wherein the bus controllers and the peripheral devices are enabled by the clock signal.
Claim 7
Dependent Claim
66 words
The power management method of claim 1 further comprising the step of checking after the clock signal is stopped for a first time period and again reading to obtain a third time constant and stopping the sending of the clock signal again when the third time constant is smaller than the first time constant plus a predetermined third time constant greater than or equal to zero.
Claim 8
Dependent Claim
27 words
The power management method of claim 6, wherein the clock signal is supplied from the PMU controller for a second time period to execute the checking process.
Claim 9
Dependent Claim
19 words
The power management method of claim 7, wherein the second time period is shorter than the first time period.
Claim 10
Dependent Claim
15 words
The power management method of claim 6 further comprising a plurality of the checking steps.
Claim 11
Dependent Claim
262 words
A computer arrangement, comprising: a plurality of Peripheral Component Interconnect (PCI) buses, a plurality of bus controllers for controlling the PCI buses, each bus controller including a signal generator for generating an asynchronous signal, a plurality of peripheral devices connected to the PCI buses, each peripheral device including a signal generator for generating an asynchronous signal, a power management unit (PMU) controller connected to a first of the PCI buses, the PMU controller including a signal detector for detecting an asynchronous signal generated by any one of the bus controllers or peripheral devices, the PMU controller stopping the sending of a clock signal to the bus controllers and the peripheral devices when all of the plurality of PCI buses are idle and restarting the clock signal when an asynchronous signal is detected by the PMU controller, and a memory device provided by the PMU controller for storing a head configuration and a first time constant corresponding to a specific one of the peripheral devices and a second time constant corresponding to the length of time needed for the PMU controller to read the head configuration from the specific peripheral device, the specific peripheral device being one of the peripheral devices which is connected to the PCI bus which has the most intervening buses between itself and the first PCI bus, wherein if the second time constant is smaller than the first time constant plus a predetermined time constant greater than or equal to zero, the PMU controller stops the sending of the clock signal to the bus controllers and the peripheral devices.
Claim 12
Dependent Claim
262 words
A computer arrangement, comprising: a plurality of Peripheral Component Interconnect (PCI) buses, a plurality of bus controllers for controlling the PCI buses, each bus controller including a signal generator for generating an asynchronous signal, a plurality of peripheral devices connected to the PCI buses, each peripheral device including a signal generator for generating an asynchronous signal, a power management unit (PMU) controller connected to a first of the PCI buses, the PMU controller including a signal detector for detecting an asynchronous signal generated by any one of the bus controllers or peripheral devices, the PMU controller stopping the sending of a clock signal to the bus controllers and the peripheral devices when all of the plurality of PCI buses are idle and restarting the clock signal when an asynchronous signal is detected by the PMU controller, and a memory device provided by the PMU controller for storing a head configuration and a first time constant corresponding to a specific one of the peripheral devices and a second time constant corresponding to the length of time needed for the PMU controller to read the head configuration from the specific peripheral device, the specific peripheral device being one of the peripheral devices which is connected to the PCI bus which has the most intervening buses between itself and the first PCI bus, wherein if the second time constant is smaller than the first time constant plus a predetermined time constant greater than or equal to zero, the PMU controller stops the sending of the clock signal to the bus controllers and the peripheral devices.
Claim 13
Dependent Claim
264 words
A computer arrangement, comprising: a plurality of Peripheral Component Interconnect (PCI) buses, a plurality of bus controllers for controlling the PCI buses, each bus controller including a signal generator for generating an asynchronous signal, a plurality of peripheral devices connected to the PCI buses, each peripheral device including a signal generator for generating an asynchronous signal, a power management unit (PMU) controller connected to a first of the PCI buses, the PMU controller including a signal detector for detecting an asynchronous signal generated by any one of the bus controllers or peripheral devices, the PMU controller stopping the sending of a clock signal to the bus controllers and the peripheral devices when all of the plurality of first PCI buses are idle and restarting the clock signal when an asynchronous signal is detected by the PMU controller, and a memory device provided by the PMU controller for storing a head configuration and a first time constant corresponding to a specific one of the peripheral devices and a second time constant corresponding to the length of time needed for the PMU controller to read the head configuration from the specific peripheral device, the first time constant determined by the time needed for the PMU controller to read the head configuration when all the peripheral devices other than the specific peripheral device are disabled, wherein if the second time constant is smaller than the first time constant plus a predetermined time constant greater that or equal to zero, the PMU controller stops the sending of the clock signal to the bus controllers and the peripheral devices.
Claim 14
Dependent Claim
264 words
A computer arrangement, comprising: a plurality of Peripheral Component Interconnect (PCI) buses, a plurality of bus controllers for controlling the PCI buses, each bus controller including a signal generator for generating an asynchronous signal, a plurality of peripheral devices connected to the PCI buses, each peripheral device including a signal generator for generating an asynchronous signal, a power management unit (PMU) controller connected to a first of the PCI buses, the PMU controller including a signal detector for detecting an asynchronous signal generated by any one of the bus controllers or peripheral devices, the PMU controller stopping the sending of a clock signal to the bus controllers and the peripheral devices when all of the plurality of first PCI buses are idle and restarting the clock signal when an asynchronous signal is detected by the PMU controller, and a memory device provided by the PMU controller for storing a head configuration and a first time constant corresponding to a specific one of the peripheral devices and a second time constant corresponding to the length of time needed for the PMU controller to read the head configuration from the specific peripheral device, the first time constant determined by the time needed for the PMU controller to read the head configuration when all the peripheral devices other than the specific peripheral device are disabled, wherein if the second time constant is smaller than the first time constant plus a predetermined time constant greater that or equal to zero, the PMU controller stops the sending of the clock signal to the bus controllers and the peripheral devices.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-12 | 2000-11-11 | 2001-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-12 | 2004-11-11 | 2005-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-12 | 2008-11-11 | 2009-05-13 | $7700.00 | Window Closed / Lapsed |