US6566760B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor storage device having memory chips in a stacked structure
Assignee: Hitachi Ltd
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Filing: 2000-09-19
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Granted: 2003-05-20
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Expires: 2020-09-19
Abstract
Abstract Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.
Inventors
- 👤 Masayasu Kawamura
- 👤 Atsushi Nakamura
- 👤 Yoshihiro Sakaguchi
- 👤 Yoshitaka Kinoshita
- 👤 Yasushi Takahashi
- 👤 Yoshihiko Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:41
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/421; H10W70/442; G; G11; G11C; G11C5/00; G11C5/02; G11C5/025; G11C5/04; G11C5/06; G11C8/00; G11C8/12; H10W70/411; H10W70/415; H10W72/00; H10W72/50; H10W72/90; H10W90/00; H10W90/811; H10W70/60; H10W72/071; H10W72/075; H10W72/541; H10W72/5449; H10W72/59; H10W72/851; H10W72/853; H10W72/865; H10W72/931; H10W72/932; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W74/00; H10W90/20; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
110 words
A memory module comprising: a plurality of semiconductor storage devices, wherein each semiconductor storage device comprises two memory chips each of which is subjected to memory accesses in 2-bit data units and capable of outputting 2-bit data units at a memory access, and both are assembled in a stacked structure so as to make memory accesses in 4-bit data units and are activated to output 4-bit data units; and wherein each of said two memory chips is provided with tape-like leads on a front surface thereof, and that, at least the front surface part is in contact with a sealing resin except a back surface of said each memory chip.
Claim 2
Dependent Claim
110 words
A memory module comprising: a plurality of semiconductor storage devices, wherein each semiconductor storage device comprises two memory chips each of which is subjected to memory accesses in 2-bit data units and capable of outputting 2-bit data units at a memory access, and both are assembled in a stacked structure so as to make memory accesses in 4-bit data units and are activated to output 4-bit data units; and wherein each of said two memory chips is provided with tape-like leads on a front surface thereof, and that, at least the front surface part is in contact with a sealing resin except a back surface of said each memory chip.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-05-19 | 2006-11-18 | 2007-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-19 | 2010-11-18 | 2011-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-19 | 2014-11-18 | 2015-05-20 | $7700.00 | Window Closed / Lapsed |