System and method for current sensing

Claim 2

A current sensing system, comprising: a current mirror circuit comprising a power switch having a number of unit cells, and a sensing switch coupled to the power switch and being a scaled ratio of said power switch; a resistive divider circuit coupled between the power switch and the sensing switch for dividing down a voltage across the power switch; and an amplifier configured to receive the divided down voltage as an input, and being coupled to the sensing switch to force a voltage across the sensing switch to be equal to the divided down voltage across the power switch, and for providing an output sensed current having a known proportion to a current through the power device.

Claim 3

The current sensing system of claim 1 , further comprising a driver and timing circuit coupled to the power switch and the resistive divider circuit to alleviate the slewing of current through the amplifier.

Claim 4

The current sensing system of claim 1 , further comprising timing logic coupled between the power switch and the resistive divider circuit for monitoring voltage at a node between the power switch and the resistive divider circuit.

Claim 5

The current sensing system of claim 1 , wherein the current mirror circuit and the amplifier are fabricated using substantially the same process.

Claim 6

The current sensing system of claim 1 , wherein the current mirror circuit, the resistive divider circuit, and the amplifier are fabricated using substantially the same process.

Claim 7

The current sensing system of claim 1 , wherein the power switch and the sensing switch each comprise a plurality of multi cell devices.

Claim 8

The current sensing system of claim 1 , wherein the power switch and the sensing switch each operate in a deep triode region.

Claim 9

A current sensing system, comprising: a power transistor having a source coupled to a voltage source for providing a current through the power transistor, and a drain coupled to a load; a sensing transistor having a source coupled to the voltage source, and a gate coupled to ground; an amplifier having an inverting input coupled to a drain of said sensing transistor and to an output of the amplifier, the amplifier configured to provide a output sensed current having a scaled proportion to the current through the power transistor; a third transistor having a source coupled to the voltage source and a drain coupled to a non-inverting input terminal of the amplifier; a fourth transistor coupled between the load and the amplifier, the fourth transistor being configured for coupling the amplifier to receive at least some portion of a voltage across the power transistor; a driver and timing circuit configured for control of the amplifier, the driver and timing circuit being coupled to a gate of the power transistor and a gate of the fourth transistor, and configured for monitoring the voltage at the drain of the power transistor to determine whether to permit the fourth transistor to provide the at least some portion of the voltage across the power transistor to the amplifier.

Claim 10

A current sensing system, comprising: a power transistor having a source coupled to a voltage source for providing a current through the power transistor, and a drain coupled to a load; a sensing transistor having a source coupled to the voltage source, and a gate coupled to ground; an amplifier having an inverting input coupled to a drain of said sensing transistor and to an output of the amplifier, the amplifier configured to provide a output sensed current having a scaled proportion to the current through the power transistor; a third transistor having a source coupled to the voltage source and a drain coupled to a non-inverting input terminal of the amplifier; a fourth transistor coupled between the load and the amplifier, the fourth transistor being configured for coupling the amplifier to receive at least some portion of a voltage across the power transistor; a driver and timing circuit configured for control of the amplifier, the driver and timing circuit being coupled to a gate of the power transistor and a gate of the fourth transistor, and configured for monitoring the voltage at the drain of the power transistor to determine whether to permit the fourth transistor to provide the at least some portion of the voltage across the power transistor to the amplifier.

Claim 11

The current sensing system of claim 8 , wherein the power transistor, sensing transistor, third transistor, fourth transistor, and amplifier are fabricated using substantially the same CMOS process.

Claim 12

The current sensing system of claim 8 , wherein the third transistor has a gate coupled to ground, and the fourth transistor has a source coupled to the non-inverting input of the amplifier and a drain coupled to the load, and wherein the third transistor and the fourth transistor are configured for dividing down the voltage across the power transistor, and the amplifier is configured to receive the divided down voltage as an input, and forcing the voltage across the sensing switch to be equal to the divided down voltage.

Claim 13

The current sensing system of claim 8 , wherein the driver and timing circuit comprises separate driver and timing logic components, the third transistor has a gate coupled to the timing logic component, the fourth transistor has a source coupled to the drain of the power transistor, the gate coupled to the timing logic component, and a drain coupled to the non-inverting input of the amplifier, and wherein the timing logic components is configured for monitoring the voltage at the drain of the power transistor to determine whether to permit the fourth transistor to provide the voltage at the drain of the power transistor to the amplifier.

Claim 14

The current sensing system of claim 8 , wherein the current system further includes: a third switch coupled to the non-inverting input of the amplifier, wherein the amplifier comprises as a common gate amplifier.

Claim 15

The current sensing system of claim 8 , wherein the amplifier includes: a gain stage comprising a fourth switch and a fifth switch, each configured as low voltage devices having a higher transconductance, and having common-gate connections, the fifth switch being connected as a diode device, the fourth switch having a source configured as a non-inverting input terminal, and the fifth switch having a source configured as an inverting input terminal; a cascode stage comprising a sixth switch and a seventh switch, each configured as high voltage devices having a lower transconductance, and having common-gate connections, the sixth switch being connected as a diode device, the seventh switch having a source coupled to a drain of the fourth switch, and the seventh switch having a source coupled to a drain of the fifth switch; a first current source coupled between a drain of the sixth switch and ground, and a second current source coupled between a drain of the seventh switch and ground; an eighth switch having-a source coupled to the inverting input terminal, a gate coupled to the drain of said fifth switch; and a ninth switch having a source coupled to a drain of said eighth switch, a gate coupled to the drain of said sixth switch, and a drain configured for providing an output for the amplifier, wherein the amplifier is configured such that as a voltage at the inverting input terminal increases, a gate-source voltage across the ninth switch will increase to facilitate the tracking of the inverting input terminal by the non-inverting terminal.

Claim 16

A current sensing system, comprising: a power transistor having a source coupled to a voltage source for providing a current through the power transistor, and a drain coupled to a load; a sensing transistor having a source coupled to the voltage source, and a gate coupled to ground an amplifier having an inverting input coupled to a drain of said sensing transistor and to an output of the amplifier, the amplifier configured to provide a output sensed current having a scaled proportion to the current through the power transistor; a third transistor having a source coupled to the voltage source and a drain coupled to a non-inverting input terminal of the amplifier; a fourth transistor having a source coupled to the drain of the power transistor and a drain coupled to the non-inverting input terminal of the amplifier, the fourth transistor being configured for decoupling the amplifier from receiving a voltage at the drain of the power transistor; a driver circuit configured for control of the amplifier, the driver circuit being coupled to a gate of the power transistor; and a timing logic device for controlling operation of the third transistor and the fourth transistor and being coupled to gates of the third transistor and the fourth transistor and configured for monitoring the voltage at the drain of the power transistor to determine whether to permit the fourth transistor to provide the voltage at the drain of the power transistor to the amplifier.

Claim 17

A current sensing system, comprising: a power transistor having a source coupled to a voltage source for providing a current through the power transistor, and a drain coupled to a load; a sensing transistor having a source coupled to the voltage source, and a gate coupled to ground an amplifier having an inverting input coupled to a drain of said sensing transistor and to an output of the amplifier, the amplifier configured to provide a output sensed current having a scaled proportion to the current through the power transistor; a third transistor having a source coupled to the voltage source and a drain coupled to a non-inverting input terminal of the amplifier; a fourth transistor having a source coupled to the drain of the power transistor and a drain coupled to the non-inverting input terminal of the amplifier, the fourth transistor being configured for decoupling the amplifier from receiving a voltage at the drain of the power transistor; a driver circuit configured for control of the amplifier, the driver circuit being coupled to a gate of the power transistor; and a timing logic device for controlling operation of the third transistor and the fourth transistor and being coupled to gates of the third transistor and the fourth transistor and configured for monitoring the voltage at the drain of the power transistor to determine whether to permit the fourth transistor to provide the voltage at the drain of the power transistor to the amplifier.

Claim 18

The current sensing system according to claim 14 , the third transistor being configured as a resistive element such that the amplifier can remain biased when the power transistor is not operating.

Claim 19

The current sensing system according to claim 14 , wherein the power transistor, the sense transistor, the third transistor and the fourth transistor are fabricated using the substantially the same process.

Claim 20

The current sensing system according to claim 14 , wherein the power transistor and the sense transistor comprise multi-cell devices.

Claim 21

The current sensing system according to claim 14 , further comprising a follower transistor having a source coupled to the drain of the sense transistor, a gate coupled to the output of the amplifier, and a drain configured to provide the output sensed current.

Claim 22

The current sensing system of claim 14 , wherein the amplifier includes: a first switch coupled to the inverting input of the amplifier; a second switch coupled to the non-inverting input of the amplifier, wherein the first and second switches share a common gate and the second switch is diode connected; a third switch coupled to the first switch and the non-inverting input of the amplifier; a first current source coupled to the first and third switches; a second current source coupled to the second switch; and an output providing the output sensed current.

Claim 23

The current sensing system of claim 19 , wherein the amplifier further includes: a fourth switch coupled between the first switch and the first current source for buffering; a fifth switch coupled between the second switch and the second current source for buffering; and a sixth switch coupled between the non-inverting input of the amplifier, the second switch, and the third switch for providing a voltage to the third switch.

Claim 24

A current sensing system, comprising: a first switch having first, second, and third terminals, wherein the first terminal is coupled to an input voltage and the second terminal is coupled to a driver for control of the first switch, and the third terminal is coupled to a load device; a second switch having fourth, fifth, and sixth terminals, wherein the fourth terminal is coupled to the input voltage, the fifth terminal is coupled to ground, and wherein a resistance of the second switch is a proportion of a resistance of the first switch; an amplifier having inverting and non-inverting inputs and an amplifier output, wherein the inverting input is coupled to the sixth terminal and the amplifier output; and a divider circuit comprising a third transistor and a fourth transistor, wherein the third transistor and fourth transistor comprise resistive elements, the third transistor having a source coupled to the input voltage, a gate coupled to ground, and a drain coupled to the non-inverting input of the amplifier, and the fourth transistor having a source coupled to the drain of the third transistor, a gate coupled to the driver for control of the fourth transistor, and a drain coupled to the load device, and wherein the divider circuit is configured for dividing down a voltage across the first switch to facilitate scaling down of a current passing through the first switch being sensed at the output of the amplifier.

Claim 25

A current sensing system, comprising: a first switch having first, second, and third terminals, wherein the first terminal is coupled to an input voltage and the second terminal is coupled to a driver for control of the first switch, and the third terminal is coupled to a load device; a second switch having fourth, fifth, and sixth terminals, wherein the fourth terminal is coupled to the input voltage, the fifth terminal is coupled to ground, and wherein a resistance of the second switch is a proportion of a resistance of the first switch; an amplifier having inverting and non-inverting inputs and an amplifier output, wherein the inverting input is coupled to the sixth terminal and the amplifier output; and a divider circuit comprising a third transistor and a fourth transistor, wherein the third transistor and fourth transistor comprise resistive elements, the third transistor having a source coupled to the input voltage, a gate coupled to ground, and a drain coupled to the non-inverting input of the amplifier, and the fourth transistor having a source coupled to the drain of the third transistor, a gate coupled to the driver for control of the fourth transistor, and a drain coupled to the load device, and wherein the divider circuit is configured for dividing down a voltage across the first switch to facilitate scaling down of a current passing through the first switch being sensed at the output of the amplifier.

Claim 26

The current sensing system according to claim 21 , wherein the amplifier comprises a common-gate amplifier, and wherein the current sensing system further comprises a current common-mode transistor having a source coupled to the source of the fourth transistor, a gate coupled to ground, and a drain coupled to a non-inverting input of the amplifier, and being configured for biasing the amplifier.

Claim 27

The current sensing system of claim 21 , wherein the first and second switches, the divider circuit, and the amplifier are fabricated using substantially the same process.

Claim 32

The method according to claim 25 , wherein the first switch, second switch and amplifier are configured in a current mirror arrangement.

Claim 33

The method according to claim 25 , wherein the second switch and the first switch comprise transistors scaled on the basis of a W/L ratio.

Claim 34

The method of claim 25 , further comprising the steps of: using a divider circuit to scale down the voltage across the first switch; configuring the first and second switches as low voltage devices; and configuring the amplifier as a high-speed amplifier.

Claim 35

The method of claim 25 , further comprising the step of monitoring the voltage across the first switch to determine whether to couple a third transistor to the amplifier to receive the scaled down voltage.

Claim 38

A current sensing system, comprising: a first switch coupled to first and second resistive elements, where the first and second resistive elements scale the current output from the first switch; a second switch coupled to the first switch for mirroring the current output from the first switch; and an amplifier coupled between the first and second resistive elements and the second switch for sensing current, wherein the amplifier includes: a third switch coupled to the inverting input of the amplifier; a fourth switch coupled to the non-inverting input of the amplifier, wherein the third and fourth switches share a common gate and the fourth switch is diode connected; a fifth switch coupled to the third switch and the non-inverting input of the amplifier; a first current source coupled to the third and fifth switches; a second current source coupled to the fourth switch; and an output to the amplifier for providing an output voltage.

Claim 39

A current sensing system, comprising: a first switch coupled to first and second resistive elements, where the first and second resistive elements scale the current output from the first switch; a second switch coupled to the first switch for mirroring the current output from the first switch; and an amplifier coupled between the first and second resistive elements and the second switch for sensing current, wherein the amplifier includes: a third switch coupled to the inverting input of the amplifier; a fourth switch coupled to the non-inverting input of the amplifier, wherein the third and fourth switches share a common gate and the fourth switch is diode connected; a fifth switch coupled to the third switch and the non-inverting input of the amplifier; a first current source coupled to the third and fifth switches; a second current source coupled to the fourth switch; and an output to the amplifier for providing an output voltage.

Claim 40

A current sensing system, comprising: a first switch having first, second, and third terminals, wherein the first terminal is coupled to an input voltage and the second terminal is coupled to a driver; a second switch having fourth, fifth, and sixth terminals, wherein the fourth terminal is coupled to the input voltage, the fifth terminal is coupled to an amplifier, and the third terminal is coupled to ground, and wherein the current through the second switch is a scaled current through the first switch; the amplifier having inverting and non-inverting inputs and an amplifier output, wherein the inverting input is coupled to the fifth terminal and the amplifier output, and wherein the amplifier includes: a third switch coupled to the inverting input of the amplifier; a fourth switch coupled to the non-inverting input of the amplifier, wherein the third and fourth switches share a common gate and the fourth switch is diode connected; a fifth switch coupled to the third switch and the non-inverting input of the amplifier; a first current source coupled to the third and fifth switches; a second current source coupled to the fourth switch; and an output to the amplifier for providing an output voltage; and a divider circuit coupled between the third terminal and the non-inverting input of the amplifier for scaling the current through the first switch.

Claim 41

A current sensing system, comprising: a first switch having first, second, and third terminals, wherein the first terminal is coupled to an input voltage and the second terminal is coupled to a driver; a second switch having fourth, fifth, and sixth terminals, wherein the fourth terminal is coupled to the input voltage, the fifth terminal is coupled to an amplifier, and the third terminal is coupled to ground, and wherein the current through the second switch is a scaled current through the first switch; the amplifier having inverting and non-inverting inputs and an amplifier output, wherein the inverting input is coupled to the fifth terminal and the amplifier output, and wherein the amplifier includes: a third switch coupled to the inverting input of the amplifier; a fourth switch coupled to the non-inverting input of the amplifier, wherein the third and fourth switches share a common gate and the fourth switch is diode connected; a fifth switch coupled to the third switch and the non-inverting input of the amplifier; a first current source coupled to the third and fifth switches; a second current source coupled to the fourth switch; and an output to the amplifier for providing an output voltage; and a divider circuit coupled between the third terminal and the non-inverting input of the amplifier for scaling the current through the first switch.

Claim 42

A current sensing system, comprising: a power transistor having a source coupled to a voltage source for providing a current through the power transistor, and a drain coupled to a load; a sensing transistor having a source coupled to the voltage source, and a gate coupled to ground; an amplifier having an inverting input coupled to a drain of said sensing transistor and to an output of the amplifier, the amplifier configured to provide a output sensed current having a scaled proportion to the current through the power transistor; a third transistor having a source coupled to the voltage source and a drain coupled to a non-inverting input terminal of the amplifier; a fourth transistor coupled between the load and the amplifier, the fourth transistor being configured for decoupling the amplifier from receiving a voltage at the drain of the power transistor; a driver and timing circuit configured for control of the amplifier, the driver and timing circuit being coupled to a gate of the power transistor and a gate of the fourth transistor, and configured for monitoring the voltage at the drain of the power transistor to determine whether to permit the fourth transistor to provide the voltage at the drain of the power transistor to the amplifier.

Claim 43

A current sensing system, comprising: a power transistor having a source coupled to a voltage source for providing a current through the power transistor, and a drain coupled to a load; a sensing transistor having a source coupled to the voltage source, and a gate coupled to ground; an amplifier having an inverting input coupled to a drain of said sensing transistor and to an output of the amplifier, the amplifier configured to provide a output sensed current having a scaled proportion to the current through the power transistor; a third transistor having a source coupled to the voltage source and a drain coupled to a non-inverting input terminal of the amplifier; a fourth transistor coupled between the load and the amplifier, the fourth transistor being configured for decoupling the amplifier from receiving a voltage at the drain of the power transistor; a driver and timing circuit configured for control of the amplifier, the driver and timing circuit being coupled to a gate of the power transistor and a gate of the fourth transistor, and configured for monitoring the voltage at the drain of the power transistor to determine whether to permit the fourth transistor to provide the voltage at the drain of the power transistor to the amplifier.