Method and apparatus for digital voltage regulation

Claim 3

The method of claim 1, wherein steps (a) through (c) are iterated.

Claim 4

The method of claim 1, wherein steps (a) through (c) are iterated at a clock frequency f clock which is an significantly faster than a desired switching frequency f switch of the switching circuit.

Claim 5

The method of claim 1, wherein calculating the total desired output current includes determining the total current passing through the switching circuits and determining a capacitive current flowing to or from capacitors coupled to the output terminal.

Claim 6

The method of claim 4, wherein determining the total current passing through the switching circuits includes summing the estimated current for each inductor.

Claim 7

The method of claim 4, wherein determining the capacitive current includes measuring a change in the output voltage.

Claim 8

The method of claim 6, wherein the capacitive current is calculated from the following equation: ##EQU13## where C is the total capacitance of the capacitors coupled to the output terminal, ΔV out is the change in the output voltage over a clock cycle, and ΔT is the duration of the clock cycle.

Claim 9

The method of claim 4, wherein calculating the total desired output current further includes determining an adjustment current for correcting an error in the output voltage.

Claim 10

The method of claim 8, wherein the adjustment current is proportional to a difference between the output voltage and a desired voltage.

Claim 11

The method of claim 9, further comprising increasing the desired voltage when the current is higher than a predetermined current level and decreasing the desired voltage when the current is lower than the predetermined current level.

Claim 12

The method of claim 1, further comprising determining a number of active switching circuits.

Claim 13

The method of claim 11, wherein the number of active switching circuits is generally proportional to the total desired current.

Claim 14

The method of claim 12, wherein a new number of active slaves is based on an old number of active switching circuits and the total desired current.

Claim 15

The method of claim 12, wherein the determination of the number of active slaves includes a hysteresis effect to avoid excessive changing of the number of active switching circuits.

Claim 16

The method of claim 11, further comprising calculating an individual desired output current for each switching circuit, the sum of the individual desired output currents being equal to the total desired output current.

Claim 17

The method of claim 15, wherein the individual desired current for the active switching circuits is approximately equal to the total desired current divided by the number of active switching circuits.

Claim 18

The method of claim 15, wherein the individual desired current for the inactive slaves is approximately zero.

Claim 19

The method of claim 1, wherein calculating the desired total current includes determining a desired voltage which is within a voltage tolerance of a nominal voltage.

Claim 20

The method of claim 18, wherein determining the desired voltage includes setting the desired voltage above the nominal voltage when the current is near a maximum current and setting the desired voltage below the nominal voltage when the current is near zero.

Claim 21

The method of claim 18, wherein determining the desired voltage includes adjusting the desired voltage by a term that is proportional to the difference between the current voltage and the desired voltage from a previous clock cycle.

Claim 22

The method of claim 20, wherein the desired voltage V desired [n+1] for clock cycle n+1 is determined by the following equation: ##EQU14## where V nom is a nominal voltage, V desired [n] is the desired voltage from the clock cycle n, I load is the current passing through the load, I max is the maximum current permitted through the load, ΔV swing is a change in voltage permitted by the voltage tolerance, and c 1 and c 2 are feedback constants.

Claim 23

A voltage regulator having an input terminal to be coupled to an input voltage source and an output terminal to be coupled to a load, comprising: a) a plurality of switching circuit to intermittently couple the input terminal and the output terminal in response to a digital control signal; b) a plurality of filters to provide a generally DC output voltage at the output terminal, each filter including an inductor; c) a plurality of current sensors to generate a plurality of feedback signals derived from the currents passing through the switching circuits; and d) a digital controller which receives and uses the plurality of feedback signals to i) calculate an estimated current for each switching circuit, each estimated current representing a current passing through the inductor associated with the switching circuit, ii) calculate a total desired output current to pass through the inductors which will maintain an output voltage at the output terminal substantially constant, and iii) generate the digital control signal based on the estimated current and the total desired output current so that a total current passing through the inductors is approximately equal to the total desired output current.

Claim 24

A voltage regulator having an input terminal to be coupled to an input voltage source and an output terminal to be coupled to a load, comprising: a) a plurality of switching circuit to intermittently couple the input terminal and the output terminal in response to a digital control signal; b) a plurality of filters to provide a generally DC output voltage at the output terminal, each filter including an inductor; c) a plurality of current sensors to generate a plurality of feedback signals derived from the currents passing through the switching circuits; and d) a digital controller which receives and uses the plurality of feedback signals to i) calculate an estimated current for each switching circuit, each estimated current representing a current passing through the inductor associated with the switching circuit, ii) calculate a total desired output current to pass through the inductors which will maintain an output voltage at the output terminal substantially constant, and iii) generate the digital control signal based on the estimated current and the total desired output current so that a total current passing through the inductors is approximately equal to the total desired output current.