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US6552927B2
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MRAM architecture and system
Assignee: NXP USA Inc
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Filing: 2002-05-08
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Granted: 2003-04-22
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Expires: 2022-05-08
Abstract
Abstract A magnetoresistive memory fabricated on a common substrate. The memory including first and second spaced apart magnetoresistive memory arrays each including a plurality of MTJ memory cells arranged in rows and columns and a plurality of word/digit lines associated with the rows of magnetoresistive memory cells of each of the arrays. Switching circuitry is positioned on the substrate between the first and second arrays and designed to select a word/digit line in one of the first and second arrays. A current source is positioned on the substrate adjacent and coupled to the switching circuitry for supplying programming current to the selected word/digit line.
Inventors
- 👤 Peter K. Naji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:48
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/02; G11C11/14; G11C11/15; G11C11/16; G11C11/165; G11C11/1653; G11C11/1657
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
160 words
A method of operating a magnetoresistive memory comprising the steps of: providing a macro portion of a magnetoresistive memory including a plurality of magnetoresistive memory cells arranged in rows and columns, the memory array including a reference column of magnetoresistive memory cells, a plurality of word/digit lines one each magnetically associated with each row of magnetoresistive memory cells, a plurality of bit lines one each magnetically associated with each column of magnetoresistive memory cells, and first and second current source/sinks attached to opposite ends of each of the plurality of bit lines; initializing all bit lines during a first time period and selecting a specific bit line and word/digit line during the first time period in response to the application of an address; and flowing program current through the selected word/digit lines and bit lines during a subsequent time period to store data in a magnetoresistive memory cell positioned at a junction of the selected bit line and word/digit line.
Claim 2
Independent Claim
160 words
A method of operating a magnetoresistive memory comprising the steps of: providing a macro portion of a magnetoresistive memory including a plurality of magnetoresistive memory cells arranged in rows and columns, the memory array including a reference column of magnetoresistive memory cells, a plurality of word/digit lines one each magnetically associated with each row of magnetoresistive memory cells, a plurality of bit lines one each magnetically associated with each column of magnetoresistive memory cells, and first and second current source/sinks attached to opposite ends of each of the plurality of bit lines; initializing all bit lines during a first time period and selecting a specific bit line and word/digit line during the first time period in response to the application of an address; and flowing program current through the selected word/digit lines and bit lines during a subsequent time period to store data in a magnetoresistive memory cell positioned at a junction of the selected bit line and word/digit line.
Claim 3
Dependent Claim
37 words
A method as claimed in claim 1 including a step of coupling the first and second current source/sinks to the selected bit line for flowing the program current through the selected bit line in a selected direction.
Claim 4
Dependent Claim
68 words
A method as claimed in claim 1 including steps of prebiasing all bit lines during a second time period subsequent to the first time period and different than the subsequent time period, and reading data stored in a magnetoresistive memory cell positioned at a junction of the selected bit line and word/digit line subsequent to the first and second time periods and different than the subsequent time period.
Claim 5
Dependent Claim
40 words
A method as claimed in claim 3 including a step of coupling a ground to at least the magnetoresistive memory cell positioned at the junction of the selected bit line and word/digit line prior to the step of reading data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-04-21 | 2006-10-21 | 2007-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-04-21 | 2010-10-21 | 2011-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-04-21 | 2014-10-21 | 2015-04-22 | $7700.00 | Window Closed / Lapsed |