Current conveyor and method for readout of MTJ memories

Claim 2

A current conveyor for readout of a magnetic tunneling junction memory cell comprising: a data readout line connected to at least one magnetic tunneling junction memory cell; a current source; a transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal being coupled to the current source and the second current terminal being coupled to the data readout line; and an operational amplifier having an output terminal connected to the control terminal of the transistor, the operational amplifier having a first input terminal connected to the data readout line and a second input terminal adapted to be coupled to a bias voltage.

Claim 3

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 1 wherein the first input terminal of the operational amplifier is a negative input terminal and the second input terminal is a positive input terminal.

Claim 4

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 1 wherein the transistor is a field effect transistor.

Claim 5

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 1 wherein the first current terminal of the transistor is further coupled through an impedance and a semiconductor switch to a current return.

Claim 6

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 4 wherein the impedance is a resistance which is larger than a resistance of the at least one magnetic tunneling junction memory cell.

Claim 7

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 4 wherein the semiconductor switch is a field effect transistor with a control terminal connected to receive a data readout line enable signal.

Claim 8

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 1 further including a second transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal of the second transistor being coupled to the current source and the second current terminal of the second transistor being coupled to a current return, and the cell further including a second operational amplifier having an output terminal connected to the control terminal of the second transistor, the second operational amplifier having a first input terminal connected to the current source and a second input terminal adapted to be coupled to a second bias voltage.

Claim 9

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 7 wherein the first input terminal of the second operational amplifier is a negative input terminal and the second input terminal of the second operational amplifier is a positive input terminal.

Claim 10

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 7 wherein the second transistor is a field effect transistor with a control terminal connected to provide a data readout signal.

Claim 11

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 9 including in addition a circuit for providing a reference voltage output signal, and a comparator having a first input terminal connected to the control terminal of the second transistor and a second input terminal connected to receive the reference voltage output signal.

Claim 12

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 10 wherein the circuit for providing the reference voltage output signal includes: a second data readout line connected to at least one magnetic tunneling junction memory cell; a current source; a third transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal of the third transistor being coupled to the current source and the second current terminal of the third transistor being coupled to the data readout line; and a third operational amplifier having an output terminal connected to the control terminal of the third transistor, the third operational amplifier having a first input terminal connected to the second data readout line and a second input terminal adapted to be coupled to a bias voltage.

Claim 13

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 11 wherein the circuit for providing the reference voltage output signal further includes a fourth transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal of the fourth transistor being coupled to the current source and the second current terminal of the fourth transistor being coupled to a current return, and the cell further including a fourth operational amplifier having an output terminal connected to the control terminal of the fourth transistor, the fourth operational amplifier having a first input terminal connected to the current source and a second input terminal adapted to be coupled to a second bias voltage.

Claim 14

A current conveyor for readout of a magnetic tunneling junction memory cell comprising: a data readout line connected to at least one magnetic tunneling junction memory cell; a current source; a first transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal of the first transistor being coupled to the current source and the second current terminal of the first transistor being coupled to the data readout line; and a first operational amplifier having an output terminal connected to the control terminal of the first transistor, the first operational amplifier having a first input terminal connected to the first current output terminal of the first transistor and a second input terminal adapted to be coupled to a bias voltage; a second transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal of the second transistor being coupled to the current source and the second current terminal of the second transistor being coupled to a current return, and the cell further including a second operational amplifier having an output terminal connected to the control terminal of the second transistor, the second operational amplifier having a first input terminal connected to the current source and a second input terminal adapted to be coupled to a second bias voltage; a circuit for providing a reference voltage output signal; and a comparator having a first input terminal connected to the control terminal of the second transistor and a second input terminal connected to receive the reference voltage output signal.

Claim 15

A current conveyor for readout of a magnetic tunneling junction memory cell comprising: a data readout line connected to at least one magnetic tunneling junction memory cell; a current source; a first transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal of the first transistor being coupled to the current source and the second current terminal of the first transistor being coupled to the data readout line; and a first operational amplifier having an output terminal connected to the control terminal of the first transistor, the first operational amplifier having a first input terminal connected to the first current output terminal of the first transistor and a second input terminal adapted to be coupled to a bias voltage; a second transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal of the second transistor being coupled to the current source and the second current terminal of the second transistor being coupled to a current return, and the cell further including a second operational amplifier having an output terminal connected to the control terminal of the second transistor, the second operational amplifier having a first input terminal connected to the current source and a second input terminal adapted to be coupled to a second bias voltage; a circuit for providing a reference voltage output signal; and a comparator having a first input terminal connected to the control terminal of the second transistor and a second input terminal connected to receive the reference voltage output signal.

Claim 16

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 13 wherein the circuit for providing the reference voltage output signal includes: a second data readout line connected to at least one magnetic tunneling junction memory cell; a current source; a third transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal of the third transistor being coupled to the current source and the second current terminal of the third transistor being coupled to the data readout line; and a third operational amplifier having an output terminal connected to the control terminal of the third transistor, the third operational amplifier having a first input terminal connected to the second data readout line and a second input terminal adapted to be coupled to a bias voltage.

Claim 17

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 14 wherein the circuit for providing the reference voltage output signal further includes a fourth transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal of the fourth transistor being coupled to the current source and the second current terminal of the fourth transistor being coupled to a current return, and the cell further including a fourth operational amplifier having an output terminal connected to the control terminal of the fourth transistor, the fourth operational amplifier having a first input terminal connected to the current source and a second input terminal adapted to be coupled to a second bias voltage.

Claim 18

A current conveyor for readout of a magnetic tunneling junction memory cell comprising: an array of magnetic tunneling junction memory cells arranged in rows and columns; a plurality of data readout lines associated with the array, each data readout line being connected to at least one magnetic tunneling junction memory cell of the array of cells; each data readout line having a current conveyor coupled thereto and each current conveyor including a current source, a transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal being coupled to the current source and the second current terminal being coupled to the data readout line, and an operational amplifier having an output terminal connected to the control terminal of the transistor, the operational amplifier having a first input terminal connected to the data readout line and a second input terminal adapted to be coupled to a bias voltage.

Claim 19

A current conveyor for readout of a magnetic tunneling junction memory cell comprising: an array of magnetic tunneling junction memory cells arranged in rows and columns; a plurality of data readout lines associated with the array, each data readout line being connected to at least one magnetic tunneling junction memory cell of the array of cells; each data readout line having a current conveyor coupled thereto and each current conveyor including a current source, a transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal being coupled to the current source and the second current terminal being coupled to the data readout line, and an operational amplifier having an output terminal connected to the control terminal of the transistor, the operational amplifier having a first input terminal connected to the data readout line and a second input terminal adapted to be coupled to a bias voltage.

Claim 20

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 16 wherein each current conveyor further includes a second transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal of the second transistor being coupled to the current source and the second current terminal of the second transistor being coupled to a current return, and the cell further including a second operational amplifier having an output terminal connected to the control terminal of the second transistor, the second operational amplifier having a first input terminal connected to the current source and a second input terminal adapted to be coupled to a second bias voltage.

Claim 21

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 17 including in addition a circuit for providing a reference voltage output signal, and comparator circuitry having at least one input terminal connected to the control terminal of the second transistor of each current conveyor and a second input terminal connected to receive the reference voltage output signal.

Claim 22

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 18 wherein the circuit for providing the reference voltage output signal includes one of the data readout lines of the plurality of data readout lines and the coupled current conveyor.

Claim 23

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 19 wherein the comparator circuitry includes a pair of comparators each having one input terminal connected to receive the reference voltage and each having a second input terminal connected to the control terminal of the second transistor of two different current conveyors.

Claim 24

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 20 wherein the reference voltage has a value such that it is approximately midway between output voltages at the control terminals of the second transistor of the two different current conveyors under operating conditions.

Claim 25

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 16 wherein the first current terminal of the transistor is further coupled through an impedance and a semiconductor switch to a current return.

Claim 26

A current conveyor for readout of a magnetic tunneling junction memory cell as claimed in claim 22 wherein the impedance is a resistance which is larger than a resistance of the at least one magnetic tunneling junction memory cell.