Semiconductor memory having self-refresh function

Claim 2

A semiconductor memory for controlling a timing of refreshing a plurality of memory cells, comprising: a capacitor for holding charge; a comparison circuit for comparing the voltage of an end of said capacitor with a reference voltage; a precharge circuit having at least one transistor for precharging said capacitor, the transistor of said precharge circuit having a first electrode connected to a first power source line, a second electrode connected to the end of said capacitor and an end of a current source, and a control electrode to receive a timing control signal for controlling the switching of said precharge circuit, and wherein the other ends of said capacitor and said current source are connected to a second power source line; and said current source for discharging said capacitor, said current source having a positive temperature coefficient to increase a current to flow as temperature rises, wherein the timing of refreshing said memory cells is controlled based on a temporal change, in a voltage of said capacitor.

Claim 3

A semiconductor memory as claimed in claim 1, wherein said semiconductor memory is a dynamic random access memory having a self-refresh function and controlling a timing of self-refreshing said memory cells according to a temporal change in a voltage of said capacitor.

Claim 4

A semiconductor memory as claimed in claim 1, wherein said current source includes a current source transistor operated in a subthreshold region.

Claim 5

A semiconductor memory as claimed in claim 3, wherein said current source further includes a minimum current securing circuit connected in parallel with said current source transistor.

Claim 6

A semiconductor memory as claimed in claim 4, wherein said minimum current securing circuit includes a minimum current securing transistor having a control electrode connected to said first power source line.

Claim 7

A semiconductor memory as claimed in claim 3, wherein said current source includes a control voltage adjustment circuit for adjusting a control voltage supplied to the control electrode of said current source transistor, to control the temperature coefficient of said current source.

Claim 8

A semiconductor memory as claimed in claim 6, wherein said control voltage adjustment circuit includes a first resistor connected to said first power source line, a second resistor connected to said second power source line, and a variable resistor arranged between said first resistor and said second resistor, to provide the control voltage.

Claim 9

A semiconductor memory as claimed in claim 6, wherein said current source includes current source transistors used in a subthreshold region and fuse circuit for selectively connecting said current source transistors, to adjust a current passing through said current source.

Claim 10

A semiconductor memory as claimed in claim 8, wherein said current source further includes a minimum current securing circuit connected in parallel with said current source transistors and said fuse circuit.

Claim 11

A semiconductor memory as claimed in claim 9, wherein said minimum current securing circuit includes a minimum current securing transistor having a control electrode connected to said first power source line.

Claim 12

A semiconductor memory as claimed in claim 8, wherein said current source transistors have the same size.

Claim 13

A semiconductor memory as claimed in claim 8, wherein said current source transistors have different sizes.

Claim 14

A semiconductor memory as claimed in claim 1, wherein said current source includes a control voltage adjustment circuit for adjusting a control voltage supplied to control electrodes of current source transistors, to control the temperature coefficient of said current source.

Claim 15

A semiconductor memory as claimed in claim 13, wherein said control voltage adjustment circuit includes a first resistor connected to said first power source line, a second resistor connected to said second power source line, and a variable resistor arranged between said first resistor and said second resistor, to provide the control voltage.

Claim 16

A semiconductor memory as claimed in claim 1, wherein a capacitance of the capacitor is adjustable.

Claim 17

A semiconductor memory as claimed in claim 15, wherein said capacitor includes a plurality of capacitors and a plurality of fuse circuit for selectively connecting said capacitors, to adjust the capacitance of said capacitor.

Claim 18

A semiconductor memory as claimed in claim 16, wherein said capacitors have the same capacitance.

Claim 19

A semiconductor memory as claimed in claim 16, wherein said capacitors have different capacitances.

Claim 20

A semiconductor memory controlling a timing of refreshing a plurality of memory cells, comprising: an oscillation circuit having an oscillation frequency that varies according to a current passing through said oscillation circuit; and a current control circuit having a positive temperature coefficient to increase a current as the temperature rises, said current control circuit controlling the current passing through said oscillation circuit, for controlling the timing of refreshing said memory cells, wherein: said current control circuit includes a current source having the positive temperature coefficient to increase the current as the temperature rises, a first transistor disposed between a current source circuit and a first power source line, a second transistor disposed between said current source circuit and a second power source line, and an oscillation frequency control circuit controlled by said first and second transistors and providing said oscillation circuit with a predetermined current, to control an oscillation frequency of said oscillation circuit; and said oscillation circuit is a ring oscillator having an odd number of series-connected inverters, said inverters being connected to said first power source line through first control transistors, respectively, said first control transistors being current-mirror-connected to said first transistor, said inverters being connected to said second power source line through second control transistors, respectively, said second control transistors being current-mirror-connected to said second transistor.

Claim 21

A semiconductor memory controlling a timing of refreshing a plurality of memory cells, comprising: an oscillation circuit having an oscillation frequency that varies according to a current passing through said oscillation circuit; and a current control circuit having a positive temperature coefficient to increase a current as the temperature rises, said current control circuit controlling the current passing through said oscillation circuit, for controlling the timing of refreshing said memory cells, wherein: said current control circuit includes a current source having the positive temperature coefficient to increase the current as the temperature rises, a first transistor disposed between a current source circuit and a first power source line, a second transistor disposed between said current source circuit and a second power source line, and an oscillation frequency control circuit controlled by said first and second transistors and providing said oscillation circuit with a predetermined current, to control an oscillation frequency of said oscillation circuit; and said oscillation circuit is a ring oscillator having an odd number of series-connected inverters, said inverters being connected to said first power source line through first control transistors, respectively, said first control transistors being current-mirror-connected to said first transistor, said inverters being connected to said second power source line through second control transistors, respectively, said second control transistors being current-mirror-connected to said second transistor.

Claim 22

A semiconductor memory as claimed in claim 19, wherein the output of each of said inverters in said oscillation circuit is connected to a capacitor.

Claim 23

A semiconductor memory as claimed in claim 19, wherein said current source includes a current source transistor operated in a subthreshold region.

Claim 24

A semiconductor memory as claimed in claim 21, wherein said current source further includes a minimum current securing circuit connected in parallel with said current source transistor.

Claim 25

A semiconductor memory as claimed in claim 22, wherein said minimum current securing circuit includes a minimum current securing transistor having a control electrode connected to said first power source line.

Claim 26

A semiconductor memory as claimed in claim 21, wherein said current source includes a control voltage adjustment circuit for adjusting a control voltage supplied to the control electrode of said current source transistor, to control the temperature coefficient of said current source.

Claim 27

A semiconductor memory as claimed in claim 24, wherein said control voltage adjustment circuit includes a first resistor connected to said first power source line, a second resistor connected to said second power source line, and a variable resistor arranged between said first resistor and said second resistor, to provide the control voltage.

Claim 28

A semiconductor memory as claimed in claim 19, wherein said current source includes current source transistors used in a subthreshold region and fuse circuit for selectively connecting said current source transistors, to adjust a current value passing through said current source.

Claim 29

A semiconductor memory as claimed in claim 26, wherein said current source further includes a minimum current securing circuit connected in parallel with said current source transistors and said fuse circuit.

Claim 30

A semiconductor memory as claimed in claim 27, wherein said minimum current securing circuit includes a minimum current securing transistor having a control electrode connected to said first power source line.

Claim 31

A semiconductor memory as claimed in claim 26, wherein said current source transistors have the same size.

Claim 32

A semiconductor memory as claimed in claim 26, wherein said current source transistors have different sizes.

Claim 33

A semiconductor memory as claimed in claim 26, wherein said current source includes a control voltage adjustment circuit for adjusting a control voltage supplied to the control electrodes of said current source transistors, to control the temperature coefficient of said current source.

Claim 34

A semiconductor memory as claimed in claim 31, wherein said control voltage adjustment circuit includes a first resistor connected to said first power source line, a second resistor connected to said second power source line, and a variable resistor arranged between said first resistor and second resistor, to provide the control voltage.

Claim 35

A semiconductor memory as claimed in claim 19, wherein said semiconductor memory further comprises counters having a trimming function and providing a signal whose frequency is an optional multiple of the oscillation frequency of the output of said oscillation circuit.

Claim 36

A semiconductor memory as claimed in claim 33, wherein said counters are binary counters having a trimming function, initial values to be set in said binary counters being controlled to provide the frequency that is the optional multiple of the oscillation frequency.