Patent US6532546B2 successfully refreshed from Google Patents.
US6532546B2
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Computer system for dynamically scaling busses during operation
Assignee: Hewlett Packard Development Co LP
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Filing: 2002-03-15
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Granted: 2003-03-11
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Expires: 2022-03-15
Abstract
Abstract Apparatus and method are disclosed for down scaling performance of a multibus multiprocessor computer system. One or more busses associated with one or more failed processors or devices are disabled to allow operation from remaining busses. If errors or power failure are detected in a processor or bus device the computer system may reboot and, using the apparatus and method of the present invention, the bus associated with the defective processors or devices may be disabled upon reboot. The one or more affected busses may be disabled and the computer system may be brought back up in a single-bus operational mode or a multiple bus operational mode where an alternate bus is designated as the boot bus.
Inventors
- 👤 Michael C. Sanders
- 👤 B. Tod Cox
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:13
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/2002; G06F11/2007
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
119 words
A method for controlling the operation of two or more buses in a computer system having one or more processors, the method comprising the acts of: detecting one or more failure modes associated with at least one of the two or more buses; generating a failure signal responsive to the act of detecting, the failure signal corresponding to the one or more failure modes; issuing a reset signal to reset the computer system with the at least one of the two or more buses disabled; and restarting the computer system responsive to the reset signal using a remaining one or more busses enabled and a predetermined one of the remaining one or more busses being designated a boot bus.
Claim 2
Independent Claim
119 words
A method for controlling the operation of two or more buses in a computer system having one or more processors, the method comprising the acts of: detecting one or more failure modes associated with at least one of the two or more buses; generating a failure signal responsive to the act of detecting, the failure signal corresponding to the one or more failure modes; issuing a reset signal to reset the computer system with the at least one of the two or more buses disabled; and restarting the computer system responsive to the reset signal using a remaining one or more busses enabled and a predetermined one of the remaining one or more busses being designated a boot bus.
Claim 3
Dependent Claim
33 words
The method of claim 1 , wherein the act of detecting one or more failure modes comprises the act of detecting a power failure of one or more of the plurality of processors.
Claim 4
Dependent Claim
30 words
The method of claim 1 , wherein the act of detecting one or more failure modes comprises the act of detecting a memory error on one or more memory devices.
Claim 5
Dependent Claim
34 words
The method of claim 1 , wherein the act of detecting one or more failure modes comprises the act of detecting a bus error on one or more of the two or more buses.
Claim 6
Independent Claim
69 words
A method for controlling the operation of one or more buses in a computer system having one or more processors, the method comprising: detecting a failure mode in one or more devices coupled to the one or more buses; selectively disabling the one or more busses in response to the act of detecting a failure mode; and resetting the computer system with the one or more buses being disabled.
Claim 7
Independent Claim
69 words
A method for controlling the operation of one or more buses in a computer system having one or more processors, the method comprising: detecting a failure mode in one or more devices coupled to the one or more buses; selectively disabling the one or more busses in response to the act of detecting a failure mode; and resetting the computer system with the one or more buses being disabled.
Claim 8
Dependent Claim
32 words
The method of claim 5 , wherein the act of detecting a failure mode comprises the act of detecting a power failure of one or more of the one or more processors.
Claim 9
Dependent Claim
28 words
The method of claim 5 , wherein the act of detecting a failure mode comprises the act of detecting a memory error on one or more memory devices.
Claim 10
Dependent Claim
34 words
The method of claim 5 , wherein the act of detecting one or more failure modes comprises the act of detecting a bus error on one or more of the two or more buses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-03-10 | 2006-09-09 | 2007-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-10 | 2010-09-09 | 2011-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-10 | 2014-09-09 | 2015-03-11 | $7700.00 | Window Closed / Lapsed |