Patent US6532143B2 successfully refreshed from Google Patents.
US6532143B2
Expired / Lapsed
US
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Multiple tier array capacitor
Assignee: Intel Corp
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Filing: 2000-12-29
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Granted: 2003-03-11
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Expires: 2020-12-29
Abstract
Abstract A capacitor includes multiple tiers ( 302, 304, 306, 1210, 1212, 1310, 1312, 1380 , FIGS. 3, 12, 13 ), which provide capacitance to a load at different inductance values. Each tier includes multiple layers ( 311-325, 1220, 1222, 1320, 1322, 1382 , FIGS. 3, 12, 13 ) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias ( 330, 332, 334, 1230, 1232 , FIGS. 3, 12 ) that extend through some or all of the tiers. In another embodiment, one or more tiers ( 1310, 1312 , FIG. 13 ) are located in a center region ( 1404 , FIG. 14 ) of the capacitor, and one or more other tiers ( 1380 , FIG. 13 ) are located in a peripheral region ( 1408 , FIG. 14 ) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers ( 1370 , FIG. 13 ) of patterned conductive material. The capacitors of the various embodiments can be used as discrete devices, which are mountable on or embeddable within a housing (e.g., a package, interposer, socket or PC board), or they can be integrally fabricated within the housing.
Inventors
- 👤 David G. Figueroa
- 👤 Kishore K. Chakravorty
- 👤 Huong T. Do
- 👤 Larry Eugene Mosley
- 👤 Jorge Pedro Rodriguez
- 👤 Ken Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:08
CPC Classifications
H; H01; H01G; H01G4/00; H01G4/30; H05; H05K; H05K1/00; H05K1/02; H05K1/0296; H05K1/0298; H05K1/16; H05K1/162; H10; H10W; H10W44/00; H10W44/601; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
212 words
A capacitor comprising: a first tier of capacitance, which includes multiple first layers of patterned conductive material separated by multiple first layers of dielectric material; a first number of first capacitor vias, which extend from a top surface of the capacitor through the multiple first layers of patterned conductive material and the multiple first layers of dielectric material, wherein some of the first capacitor vias make electrical contact with a first set of layers that includes every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a second set of layers that includes a remainder of the multiple first layers; a second tier of capacitance, located substantially underneath the first tier of capacitance and electrically connected to the first tier of capacitance, which includes multiple second layers of patterned conductive material separated by multiple second layers of dielectric material; and a second number of second capacitor vias, which extend through the multiple second layers of patterned conductive material and the multiple second layers of dielectric material, wherein some of the second capacitor vias make electrical contact with every other one of the multiple second layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple second layers.
Claim 2
Dependent Claim
212 words
A capacitor comprising: a first tier of capacitance, which includes multiple first layers of patterned conductive material separated by multiple first layers of dielectric material; a first number of first capacitor vias, which extend from a top surface of the capacitor through the multiple first layers of patterned conductive material and the multiple first layers of dielectric material, wherein some of the first capacitor vias make electrical contact with a first set of layers that includes every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a second set of layers that includes a remainder of the multiple first layers; a second tier of capacitance, located substantially underneath the first tier of capacitance and electrically connected to the first tier of capacitance, which includes multiple second layers of patterned conductive material separated by multiple second layers of dielectric material; and a second number of second capacitor vias, which extend through the multiple second layers of patterned conductive material and the multiple second layers of dielectric material, wherein some of the second capacitor vias make electrical contact with every other one of the multiple second layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple second layers.
Claim 3
Dependent Claim
51 words
The capacitor as claimed in claim 1 , wherein the second capacitor vias extend through the multiple first layers, wherein some of the second capacitor vias make electrical contact with the first set of layers, and others of the second capacitor vias make electrical contact with the second set of layers.
Claim 4
Dependent Claim
26 words
The capacitor as claimed in claim 2 , wherein the first number of first capacitor vias is greater than the second number of second capacitor vias.
Claim 5
Dependent Claim
37 words
The capacitor as claimed in claim 2 , wherein the second capacitor vias extend to a bottom surface of the capacitor so that electrical connections can be made to the second capacitor vias at the bottom surface.
Claim 6
Dependent Claim
88 words
The capacitor as claimed in claim 1 , further comprising: at least one additional tier of capacitance, electrically connected between the first tier of capacitance and the second tier of capacitance, which includes multiple additional layers of patterned conductive material; and additional capacitor vias, which extend through the multiple additional layers, wherein some of the additional capacitor vias make electrical contact with every other one of the multiple additional layers, and others of the additional capacitor vias make electrical contact with a remainder of the multiple additional layers.
Claim 7
Dependent Claim
15 words
The capacitor as claimed in claim 1 , wherein the capacitor is a discrete device.
Claim 8
Dependent Claim
193 words
A capacitor comprising: a first tier of capacitance, which includes multiple first layers of patterned conductive material separated by layers of dielectric material; a first number of first capacitor vias, which extend from a top surface of the capacitor through the multiple first layers, wherein some of the first capacitor vias make electrical contact with every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a remainder of the multiple first layers; a second tier of capacitance, electrically connected to the first tier of capacitance, which includes multiple second layers of patterned conductive material; and a second number of second capacitor vias, which extend through the multiple second layers, wherein some of the second capacitor vias make electrical contact with every other one of the multiple second layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple second layers, wherein the capacitor is a discrete device, and wherein the first tier of capacitance is located in a center region of the capacitor, and the second tier of capacitance is located in a peripheral region of the capacitor.
Claim 9
Dependent Claim
193 words
A capacitor comprising: a first tier of capacitance, which includes multiple first layers of patterned conductive material separated by layers of dielectric material; a first number of first capacitor vias, which extend from a top surface of the capacitor through the multiple first layers, wherein some of the first capacitor vias make electrical contact with every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a remainder of the multiple first layers; a second tier of capacitance, electrically connected to the first tier of capacitance, which includes multiple second layers of patterned conductive material; and a second number of second capacitor vias, which extend through the multiple second layers, wherein some of the second capacitor vias make electrical contact with every other one of the multiple second layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple second layers, wherein the capacitor is a discrete device, and wherein the first tier of capacitance is located in a center region of the capacitor, and the second tier of capacitance is located in a peripheral region of the capacitor.
Claim 10
Dependent Claim
15 words
The capacitor as claimed in claim 1 , wherein the capacitor is a ceramic capacitor.
Claim 11
Dependent Claim
25 words
The capacitor as claimed in claim 1 , wherein the first tier of capacitance and the second tier of capacitance are integrated within a housing.
Claim 12
Dependent Claim
203 words
A capacitor comprising: a first tier of capacitance, which includes multiple first layers of patterned conductive material separated by layers of dielectric material; a first number of first capacitor vias, which extend from a top surface of the capacitor through the multiple first layers, wherein some of the first capacitor vias make electrical contact with every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a remainder of the multiple first layers; a second tier of capacitance, electrically connected to the first tier of capacitance, which includes multiple second layers of patterned conductive material; and a second number of second capacitor vias, which extend through the multiple second layers, wherein some of the second capacitor vias make electrical contact with every other one of the multiple second layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple second layers, wherein the first tier of capacitance and the second tier of capacitance are integrated within a housing, and wherein the first tier of capacitance is located in a center region of the housing, and the second tier of capacitance is located in a peripheral region of the housing.
Claim 13
Dependent Claim
203 words
A capacitor comprising: a first tier of capacitance, which includes multiple first layers of patterned conductive material separated by layers of dielectric material; a first number of first capacitor vias, which extend from a top surface of the capacitor through the multiple first layers, wherein some of the first capacitor vias make electrical contact with every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a remainder of the multiple first layers; a second tier of capacitance, electrically connected to the first tier of capacitance, which includes multiple second layers of patterned conductive material; and a second number of second capacitor vias, which extend through the multiple second layers, wherein some of the second capacitor vias make electrical contact with every other one of the multiple second layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple second layers, wherein the first tier of capacitance and the second tier of capacitance are integrated within a housing, and wherein the first tier of capacitance is located in a center region of the housing, and the second tier of capacitance is located in a peripheral region of the housing.
Claim 14
Dependent Claim
171 words
A capacitor comprising: a first tier of capacitance located in a center region of the capacitor, which includes multiple first layers of patterned conductive material separated by layers of dielectric material; a first number of first capacitor vias, which extend from a top surface of the capacitor through the multiple first layers, wherein some of the first capacitor vias make electrical contact with every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a remainder of the multiple first layers; a second tier of capacitance located in a peripheral region of the capacitor, electrically connected to the first tier of capacitance, which includes multiple second layers of patterned conductive material; and a second number of second capacitor vias, which extend through the multiple second layers, wherein some of the second capacitor vias make electrical contact with every other one of the multiple second layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple second layers.
Claim 15
Dependent Claim
171 words
A capacitor comprising: a first tier of capacitance located in a center region of the capacitor, which includes multiple first layers of patterned conductive material separated by layers of dielectric material; a first number of first capacitor vias, which extend from a top surface of the capacitor through the multiple first layers, wherein some of the first capacitor vias make electrical contact with every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a remainder of the multiple first layers; a second tier of capacitance located in a peripheral region of the capacitor, electrically connected to the first tier of capacitance, which includes multiple second layers of patterned conductive material; and a second number of second capacitor vias, which extend through the multiple second layers, wherein some of the second capacitor vias make electrical contact with every other one of the multiple second layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple second layers.
Claim 16
Dependent Claim
15 words
The capacitor as claimed in claim 11 , wherein the capacitor is a discrete device.
Claim 17
Dependent Claim
15 words
The capacitor as claimed in claim 12 , wherein the capacitor is a ceramic capacitor.
Claim 18
Dependent Claim
25 words
The capacitor as claimed in claim 11 , wherein the first tier of capacitance and the second tier of capacitance are integrated within a housing.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-03-10 | 2006-09-09 | 2007-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-10 | 2010-09-09 | 2011-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-10 | 2014-09-09 | 2015-03-11 | $7700.00 | Window Closed / Lapsed |